24-11-2012, 01:46 PM
The Introduction of PCI Bus
Introduction of PCI Bus.ppt (Size: 375.5 KB / Downloads: 29)
In 1992,the Peripheral Component Interconnect(PCI) bus was released.
Introduced by Intel as an open architecture,it quickly became the standard for high-speed buses in the PC markets.
PCI standards addressing the usage of one of two high speed buses,either a 32-bits or a 64-bits,operating at bus speeds of up to 33MHz,or 66MHz respectively.
A PCI normally operates in a master mode(initiator in PCI terminology) and slave mode(target in PCI terminology).
Cost-Effective Technology
PCI’s standardized components and silicon have enabled huge economies of scale that make PCI products easy and inexpensive to develop.
As a result,PCI has become the universal connection standard,and has given PCs an affordable graphics capability that was unachievable with previous bus technologies.
PCI’s standardized components and silicon have enabled huge economies of scale that make PCI products easy and inexpensive to develop.
As a result,PCI has become the universal connection standard,and has given PCs an affordable graphics capability that was unachievable with previous bus technologies.
Evolving to Meet Industry Needs
Recent enhancement to PCI version 2.2 include:
PCI Hot-Plug:
Enables removal or replacement of adapter cards without having to shut down the main system,so the PCI cards are Hot-Plug capable without modification.
PCI Power Management:
The power manages by o.s.
PCI Power Management enables energy conservation in PCs,efficient mobile computing,and higher-availability PCs for off-hours tasks such as receiving faxes or Internet transmissions.
Design of PCI Arbiter
Video Grabber, which will input a raw video data. It can be NTSC, PAL or SECAM sequence or may be in XGA, SVGA or in any other format. Any color motion picture can be processed, say, at 30 frames per second or 25 frames per second. Using the PCI, we can input the raw data into the Video Codec.
Video Codec brings about the compression and reconstruction. We have an encoder and a decoder in the Codec, which brings about respectively the compression and decompression. This has to be designed in Verilog and implemented on either FPGA or ASIC.
Fire Wire is a serial bus, which can be connected up to 64K nodes. It serializes the compressed data and broadcasts the compressed bit stream. Concurrently, it can receive a compressed bit stream from external source and send it to the decoder in Video Codec for effecting decompression.
CPU (PC), which configures and coordinates the system activities via a north bridge
VERILOG CODE FOR PCI Arbiter Design
The PCI arbiter design code is presented in Verilog_code_13.1. The design module is named “pci_arbiter”. After declaring the design module, the inputs/outputs are identified. The arbiter design is a simple FSM and is realized using the case statement. All the conditional states of the request and grant signals are coded in the same order as the ASM chart and are self-explanatory. The states of the ASM chart are identified by the signal, “arbiter_state”, in the code. Priority is automatically assigned since we have used “if–else if–else” structure in the code.
module pci_arbiter ( // Declare the design module