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Calculating the Logical Effort of Gates
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The simplicity of the theory of logical effort follows from assigning to each kind of
logic gate a number—its logical effort—that describes its drive capability relative
to that of a reference inverter. The logical effort is independent of the actual size
of the logic gate, allowing one to postpone detailed calculations of transistor sizes
until after the logical effort analysis is complete.
Each logic gate is characterized by two quantities: its logical effort and its
parasitic delay. These parameters may be determined in three ways:
Using a few process parameters, one can estimate logical effort and parasitic
delay as described in this chapter. The results are sufficiently accurate for
most design work.
Using test circuit simulations, the logical effort and parasitic delay can be
simulated for various logic gates. This technique is explained in Chapter 5.
Using fabricated test structures, logical effort and parasitic delay can be
physically measured.
Before turning tomethods of calculating logical effort, we present a discussion
of different definitions and interpretations of logical effort. While these are all
equivalent, in some sense, each offers a different perspective to the design task
and each leads to different intuitions.
0Copyright c
1998, Morgan Kaufmann Publishers, Inc. This material may not be copied or
distributed without permission of the publisher.
CALCULATING THE LOGICAL EFFORT OF GATES
Definitions of logical effort
Logical effort captures enough information about a logic gate’s topology—the
network of transistors that connect the gate’s output to the power supply and to
ground—to determine the delay of the logic gate. In this section, we give three
equivalent concrete definitions of logical effort.
Definition 4.1 The logical effort of a logic gate is defined as the number of times
worse it is at delivering output current than would be an inverter with identical
input capacitance.
Any topology required to perform logic makes a logic gate less able to deliver
output current than an inverter with identical input capacitance. For one thing, a
logic gate must have more transistors than an inverter, and so to maintain equal
input capacitance, its transistors must be narrower on average and thus less able
to conduct current than those of an inverter with identical input capacitance. If its
topology requires transistors in parallel, a conservative estimate of its performance
will assume that not all of them conduct at once, and therefore that they will not
deliver as much current as could an inverter with identical input capacitance. If its
topology requires transistors in series, it cannot possibly deliver as much current
as could an inverter with identical input capacitance. Whatever the topology of
a simple logic gate, its ability to deliver output current must be worse than an
inverter with identical input capacitance. Logical effort is a measure of how much
worse.
Definition 4.2 The logical effort of a logic gate is defined as the ratio of its input
capacitance to that of an inverter that delivers equal output current.
This alternative definition is useful for computing the logical effort of a particular
topology. To compute the logical effort of a logic gate, pick transistor sizes
for it that make it as good at delivering output current as a standard inverter, and
then tally up the input capacitance of each input signal. The ratio of this input
capacitance to that of the standard inverter is the logical effort of that input to the
logic gate. The logical effort of a logic gate will depend slightly on the mobilitiy
ratio in the fabrication process used to build it. These calculations are shown in
detail later in this chapter.
Definition 4.3 The logical effort of a logic gate is defined as the slope of the
gate’s delay vs. fanout curve divided by the slope of an inverter’s delay vs. fanout
curve.
GROUPING INPUT SIGNALS 61
This alternative definition suggests an easy way to measure the logical effort of
any particular logic gate by experiements with real or simulated circuits of various
fanouts.
Grouping input signals
Because logical effort relates the input capacitance to the output drive current
available, a natural question arises: for a logic gate with multiple inputs, how
many of the input signals should we consider when computing logical effort? It
is useful to define several kinds of logical effort, depending on how input signals
are grouped. In each case, we define an input group to contain the input signals
that are relevant to the computation of logical effort:
Logical effort per input, in which logical effort measures the effectiveness
of a single input in controlling output current. The input group is the single
input in question. All of the discussion in preceding chapters uses logical
effort per input.
Logical effort of a bundle, a group of related inputs. For example, a multiplexer
requires true and complement select signals; this pair might be
grouped into a bundle. Because bundles of complementary pairs of signals
occur frequently in CMOS circuits, we adopt a special notation: s stands
for a bundle containing the true signal s and the complement signal s. The
input group of a bundle contains all the signals in the bundle.
Total logical effort, the logical effort of all inputs taken together. The input
group contains all the input signals of the logic gate.
Terminology and context determine which kind of logical effort applies. The
adjective “total” is always used when total logical effort is meant, while the other
two cases are distinguished by the signals associated with them in context. “The
total logical effort of a 2-input NAND gate” is the logical effort of both inputs taken
together, while “the logical effort of a 2-input NAND gate” is the logical effort per
input of one of its two inputs.
The logical effort of an input group is defined analogously to the logical effort
per input, shown in the previous section. The analog of Definition 4.2 is: the
logical effort gb of an input group b is just