09-02-2013, 12:02 PM
A Low-Power LFSR Architecture
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INTRODUCTION
LFSR’s are widely used in the BIST environment. In [1]
a multiphase technique is proposed to reduce the data transitions
(DTs) in both the LFSR and the circuit under test.
However, its multiphase clock generator is implemented
by a conventional Johnson counter with a complex control
logic, which requires considerable area overhead and
power dissipation. Also the employed dynamic demultiplexers
may consume much power. In this paper, we develop a
low-power multiphase clock generator, employ static demultiplexers
and propose a hybrid design to reduce the power.
The power model is based on the weighted transition count
(WTC) [2]. The internal gates of a latch consume 2 transitions
per cycle when the data changes. The clock and data
input capacitances of a latch are assumed the same as that
of a regular gate. A double-latch FF thus consumes 5 transitions
including the interconnection between latches when
the data changes.
Our design can be described as follows. First, a conventional
n-phase clock generator usually employs an n
2 -FF
Johnson counter. We propose to replace each FF with a
latch as shown in Fig. 1, where correct n-phase clock signals
can still be generated without the data transparency problem
if the odd and even latches are in complemented (lowor
high-level enabled) types and each enabled latch has the
same data as its preceding latch. With this latch-based
Johnson counter the WTC can be reduced from 2n+10 to
n
2 + 17 per cycle. Second, in a conventional k-phase shift
register (kΦSR) as shown in Fig. 2(a), the demultiplexer is
implemented by joined transmission gates, which actually
consume much power at joint out. We modify the output
stage as Fig. 2(b) shows. During phase i only Φi will be
high and only the data Dk−i may change with a probability
of 1
2. The kΦSR consumes 2 and k
2 transitions in the
demultiplexer and the data input, respectively. The active
FF thus consumes 5
2 transitions in average in its internal
gates and 2 transitions at the clock input. Therefore, the
kΦSR takes k
2+15
2 transitions per cycle.