09-02-2013, 02:32 PM
RISC Architecture
RISC Architecture.ppt (Size: 105 KB / Downloads: 150)
Problems of the Past
In the past, it was believed that hardware design was easier than compiler design
Most programs were written in assembly language
Hardware concerns of the past:
Limited and slower memory
Few registers
The Solution
Have instructions do more work, thereby minimizing the number of instructions called in a program
Allow for variations of each instruction
Usually variations in memory access
Minimize the number of memory accesses
CISC
Each instruction executes multiple low level operations
Ex. A single instruction can load from memory, perform an arithmetic operation, and store the result in memory
Smaller program size
Less memory calls
The Search for RISC
Compilers became more prevalent
The majority of CISC instructions were rarely used
Some complex instructions were slower than a group of simple instructions performing an equivalent task
Too many instructions for designers to optimize each one
RISC Architecture
Small, highly optimized set of instructions
Uses a load-store architecture
Short execution time
Pipelining
Many registers
Load/Store Architecture
Individual instructions to store/load data and to perform operations
All operations are performed on operands in registers
Main memory is used only to load/store instructions
RISC vs CISC
Less transistors needed in RISC
RISC processors have shorter design cycles
RISC instructions take less clock cycles than CISC instructions
CISC instructions take up to 3 to 12 times longer
Smaller instructions allowed for constants to be stored in the unused bits of the instruction
This would mean less memory calls to registers or main memory
Why CISC Persists
Most Intel and AMD chips are CISC x86
Most PC applications are written for x86
Intel spent more money improving the performance of their chips
Modern Intel and AMD chips incorporate elements of pipelining
During decoding, x86 instructions are split into smaller pieces