06-08-2013, 12:31 PM
DARLINGTON COMMON EMITTER AMPLIFIER
Aim:
To design a Darlington amplifier using BJT and to measure the gain and input resistance.
To plot the frequency response and to calculate the Gain Bandwidth Product (GBW).
Design:
Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base
current for the 2nd stage. Hence the 2nd stage IE current will be IE = (β+1)2ICO
For silicon transistor ICBO is the order of 10nA at room temperature β = 100.
Now,
IE = (101)2 X 10 nA
IE ≅ 105 nA ≅ 0.1mA
This current will get double with every 100 rise in temperature. So to reduce the effect of
ICBO the 1st stage ICBO flowing through the emitter of the 1st stage is not allowing to enter the 2nd
stage by paralleling a resistor between B & E of the 2nd stage T2. So the ICBO(β+1) will flow
through this resistance and a part of this current might flow through hie + βdcRE. This shunting
resistance will be the range of 1 to 4.7 KΩ.
Biasing Design:
Assume R2 = 10KΩ and Ic = 1mA.
Since voltage amplification is done in the Darlington transistor amplifier circuit, we
assume equal drops across VCE and load resistance RC. The ICQ = 1mA is assumed. We assume
standard supply of 12V.
Procedure:
1. Connect the circuit as per the circuit diagram.
2. Set VS = 5 mV using AFO.
3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1 MHz in regular
steps and note down the corresponding output voltage.
4. Plot the graph gain Vs frequency.
5. Calculate bandwidth from the graph.
Result:
1. The frequency response curve is plotted on a log scale.
2. From the graph the bandwidth is obtained