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VHDL Tutorial
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Introduction
The purpose of this tutorial is to describe the modeling language VHDL. VHDL in-
cludes facilities for describing logical structure and function of digital systems at a
number of levels of abstraction, from system level down to the gate level. It is intend-
ed, among other things, as a modeling language for specification and simulation. We
can also use it for hardware synthesis if we restrict ourselves to a subset that can be
automatically translated into hardware.
VHDL arose out of the United States government’s Very High Speed Integrated
Circuits (VHSIC) program. In the course of this program, it became clear that there
was a need for a standard language for describing the structure and function of inte-
grated circuits (ICs). Hence the VHSIC Hardware Description Language (VHDL) was
developed. It was subsequently developed further under the auspices of the Institute
of Electrical and Electronic Engineers (IEEE) and adopted in the form of the IEEE Stan-
dard 1076, Standard VHDL Language Reference Manual, in 1987. This first standard
version of the language is often referred to as VHDL-87.
Like all IEEE standards, the VHDL standard is subject to review at least every five
years. Comments and suggestions from users of the 1987 standard were analyzed by
the IEEE working group responsible for VHDL, and in 1992 a revised version of the
standard was proposed. This was eventually adopted in 1993, giving us VHDL-93. A
further round of revision of the standard was started in 1998. That process was com-
pleted in 2001, giving us the current version of the language, VHDL-2002.
This tutorial describes language features that are common to all versions of the
language. They are expressed using the syntax of VHDL-93 and subsequent versions.
There are some aspects of syntax that are incompatible with the original VHDL-87 ver-
sion. However, most tools now support at least VHDL-93, so syntactic differences
should not cause problems.
Modeling Digital Systems
The term digital systems encompasses a range of systems from low-level components
to complete system-on-a-chip and board-level designs. If we are to encompass this
range of views of digital systems, we must recognize the complexity with which we
are dealing. It is not humanly possible to comprehend such complex systems in their
entirety. We need to find methods of dealing with the complexity, so that we can,
with some degree of confidence, design components and systems that meet their re-
quirements.
The most important way of meeting this challenge is to adopt a systematic meth-
odology of design. If we start with a requirements document for the system, we can
design an abstract structure that meets the requirements. We can then decompose
this structure into a collection of components that interact to perform the same func-
tion. Each of these components can in turn be decomposed until we get to a level
where we have some ready-made, primitive components that perform a required
function. The result of this process is a hierarchically composed system, built from
the primitive elements.
The advantage of this methodology is that each subsystem can be designed inde-
pendently of others. When we use a subsystem, we can think of it as an abstraction
rather than having to consider its detailed composition. So at any particular stage in
the design process, we only need to pay attention to the small amount of information
relevant to the current focus of design. We are saved from being overwhelmed by
masses of detail.
VHDL Modeling Concepts
In this section, we look at the basic VHDL concepts for behavioral and structural mod-
eling. This will provide a feel for VHDL and a basis from which to work in later chap-
ters. As an example, we look at ways of describing a four-bit register, shown in
Figure 2-1.
Using VHDL terminology, we call the module reg4 a design entity, and the inputs
and outputs are ports. Figure 2-2 shows a VHDL description of the interface to this
entity. This is an example of an entity declaration. It introduces a name for the entity
and lists the input and output ports, specifying that they carry bit values (‘0’ or ‘1’) into
and out of the entity. From this we see that an entity declaration describes the external
view of the entity.