13-02-2016, 04:29 PM
ABSTRACT
In this paper deals with the comparison of the VLSI design of the carry look-ahead adder (CLAA) based 32-bit signed and unsigned integer multiplier and the VLSI design of the carry select adder (CSLA) based 32-bit signed and unsigned integer multiplier. Multiplication is a fundamental operation in most signal processing algorithms. Multipliers have large area, long latency and consume considerable power. Therefore low-power multiplier design has been an important part in low- power VLSI system design. A system’s performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the system. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is a major design issue. Carry select adder is one of the fastest adders used in many applications to perform fast arithmetic functions. This work evaluates the performance of the proposed designs in terms of delay, speed(frequency)and memory. The CLAA based multiplier uses the delay time of 99ns for performing multiplication operation where as in CSLA based multiplier also uses nearly the same delay time for multiplication operation. But the area needed for CLAA multiplier is reduced to 31 % by the CSLA based multiplier to complete the multiplication operation. Keywords-CLAA; CSLA; Delay; Area; Array Multiplier:VHDL Modeling & Simulation.
INTRODUCTION
Speed of operation is the most important constraint to be considered while designing multipliers. Due to device portability miniaturization of device should be high and power consumption should be low. High-speed data path logic systems are one of the most substantial areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the
previous bit position has been summed and a carry propagated into the next position. Ripple carry adders
exhibits the most compact design but the slowest in speed.Whereas carry look ahead is the fastest one but consumes more area. Carry select adders act as a compromise between the two adders. A new concept of hybrid adders is presented to speed up addition process[10]. The CSLA is not area
efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by
considering carry input Cin = 0and Cin = 0, then the final sum and carry are selected by the multiplexers (mux).In this project we are going to compare the performance of different adders implemented to the multipliers based on area and time needed for calculation. On comparison with the carry look-ahead adder (CLAA) based multiplier the area of calculation of the carry select adder (CSLA) based multiplier is smaller and better with nearly same delay time. Here we are dealing with the comparison in the bit range of
n*n (32*32) as input and 2n(64) bit output.