01-09-2016, 09:35 AM
Analysis of NAND/NOR Gates using Subthreshold Adiabatic Logic (SAL) for Ultra Low Power Applications
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Abstract— In this paper, in depth analysis of the NAND/NOR gates in the weak inversion regime using sub-threshold adiabatic logic (SAL) has been analyzed. As either pull up or pull down network in SAL, silicon area can be reduced significantly. The analytical expression of the power dissipation, leakage energy dissipation, and maximum and minimum output voltages is detailed here. Also the analytical expression of the optimum supply voltage and the frequency are given for the analysis. Extensive CADENCE simulations have been done to verify the analytical expressions. Simulated results are well matched with the analytical value which validates the acceptability of the proposed structure in the sub-threshold regime for the ultra low power application.
Keywords— adiabatic logic, leakage, low-power, subthreshold adiabatic logic .
I. INTRODUCTION
The ever increasing demand for design of low power devices can be addressed by implementing ultralow-power digital systems. Already in many modern types of equipment such as, mobile communication systems, bio-medical implants, sensor networks, etc., the ultralow-power logic circuits are being extensively used. In the sub-threshold logic systems the maximum operating voltage or the supply voltage VDD is much lower than the transistor’s threshold voltage VTH. In such a scenario the leakage current through the transistor is considered as the operating current. [1]-[3].
In case of the adiabatic logic circuits [4]-[7] by limiting the current across the device and by sending back the charge to the supply, the power consumption of the circuit can be reduced drastically.
Recently, the sub-threshold adiabatic logic (SAL)[7] circuit has proven to be a potential way of reducing power in digital logic circuits. The performance of SAL NAND and NOR gate has been analyzed in depth in the rest of the paper.