21-03-2012, 02:50 PM
Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding
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Introduction and Motivation
Current commercial designs integrate from10 to 100 embedded
functional and storage blocks in a single system-on-chip
(SoC), and the number is likely to increase significantly in
the near future [2, 13]. Network on chip (NoC) is viewed as
a revolutionary methodology to achieve such a high degree
of integration in a single SoC. According to the International
Technology Roadmap for Semiconductors (ITRS)
[10], signal integrity is expected to be an increasingly
critical challenge in designing SoCs. The widespread adoption
of the NoC paradigm will be possible if it addresses
system level signal integrity and reliability issues in
addition to easing the design process, and meeting all other
constraints and objectives. With shrinking feature size, one
of the major factors affecting signal integrity is transient
errors, arising due to temporary conditions of the SoC and
environmental factors.
Related Work
In recent years, there has been an evolving effort in
developing on-chip networks to integrate increasingly large
number of functional cores in a single die [2, 13]. But even
before the advent of the NoC paradigm, different research
groups investigated various coding schemes to enhance the
reliability of bus-based systems. In [32] the authors
proposed to employ data encoding to eliminate crosstalk
delay within a bus.
Data Coding in NoC Links
The common characteristic of NoC architectures is that the
functional IP blocks communicate with each other via
intelligent switches. The data communication between IP’s
in a NoC takes place in the form of packets routed through
a wormhole switching mechanism. The packets are broken
down into fixed length flow control units or flits. The
switch blocks need to store only a few flits [6, 18]. The
header flits carry the relevant routing information. Consequently
header decoding enables the establishment of a path
that the subsequent payload flits simply follow in a
pipelined fashion. The transmitted flits are encoded to
guard against possible transient errors.
DAP and MDR Schemes
The Duplicate Add Parity (DAP) scheme achieves joint
crosstalk avoidance and single error correction capability by
duplicating each bit of the n-bit flit and placing the copies
adjacent to each other to avoid crosstalk, and by also
computing a parity bit from the initial bits to enable single
error correction. Thus, the encoded flit becomes 2n+1 bits
wide [23, 30]. Modified Dual Rail (MDR) code is a simple
modification of the DR/DAP scheme, where a second copy
of the parity bit is transmitted to guard against crosstalk on
the parity bit itself [26]. Thus, the MDR encoded flit is 2n+2
bits wide. The encoder and decoder of the DAP scheme are
shown in Fig. 1. The MDR scheme is very similar and
therefore is not shown separately.
BSC Scheme
Boundary Shift Coding (BSC) is achieved by avoiding a
shared boundary between two successive code words [22].
The scheme duplicates each bit and computes an overall
parity, and then each alternate code word is given a cyclic
shift in a way that appends the parity bit to either the right
or the left of the flit after duplication. The decoding
mechanism is the same as in DAP, after carefully extracting
the parity bit from the flit depending on whether it is the
rightmost or the leftmost bit of the flit.