10-05-2012, 11:27 AM
SIMULATION OF GENERAL-PURPOSE MICROPROCESSORS USING VHDL
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. INTRODUCTION TO VHDL
VHDL stands for very high-speed integrated circuit hardware description language. Which is one of the programming language used to model a digital system by dataflow, behavioral and structural style of modeling. This language was first introduced in 1981 for the department of Defense (DoD) under the VHSIC programe. In 1983 IBM, Texas instruments and Intermetrics started to develop this language. In 1985 VHDL 7.2 version was released in 1987 IEEE standardized the language.
Describing a design:
In VHDL an entity is used to describe a hardware module.
An entity can be described using,
1. Entity declaration
2. Architecture.
3. Configuration
4. Package declaration.
5. Package body.
Design
VHDL is commonly used to write text models that describe a logic circuit. Such a model is processed by a synthesis program, only if it is part of the logic design. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called a testbench.
VHDL has file input and output capabilities, and can be used as a general-purpose language for text processing, but files are more commonly used by a simulation testbench for stimulus or verification data. There are some VHDL compilers which build executable binaries. In this case, it might be possible to use VHDL to write a testbench to verify the functionality of the design using files on the host computer to define stimuli, to interact with the user, and to compare results with those expected. However, most designers leave this job to the simulator.
It is relatively easy for an inexperienced developer to produce code that simulates successfully but that cannot be synthesized into a real device, or is too large to be practical. One particular pitfall is the accidental production of transparent latches rather than D-type flip-flops as storage elements.
VHDL is not a case sensitive language. One can design hardware in a VHDL IDE (for FPGA implementation such as Xilinx ISE, Altera Quartus, or Synopsys Synplify) to produce the RTL schematic of the desired circuit. After that, the generated schematic can be verified using simulation software which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. To generate an appropriate testbench for a particular circuit or VHDL code, the inputs have to be defined correctly. For example, for clock input, a loop process or an iterative statement is required.
The key advantage of VHDL when used for systems design is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).
Another benefit is that VHDL allows the description of a concurrent system (many parts, each with its own sub-behavior, working together at the same time). VHDL is a Dataflow language, unlike procedural computing languages such as BASIC, C, and assembly code, which all run sequentially, one instruction at a time.
A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a CPLD or FPGA, then it is the actual hardware being configured, rather than the VHDL code being "executed" as if on some form of a processor chip.
Analysis of Sequential Circuits
Very often we are given a sequential circuit and need to know its operation. The analysis of sequential circuits is the process in which we are given a sequential circuit and we want to obtain a precise description of the operation of the circuit. The description of a sequential circuit can be in the form of a next-state / output table, or a state
diagram. The steps for the analysis of sequential circuits are as follows:
1. Derive the excitation equations from the next-state logic circuit.
2. Derive the next-state equations by substituting the excitation equations into the flip-flop’s characteristic equations.
3. Derive the next-state table from the next-state equations.
4. Derive the output equations (if any) from the output logic circuit.
5. Derive the output table (if any) from the output equations.
6. Draw the state diagram from the next-state table and the output table.