11-05-2012, 11:40 AM
Low-Cost Low-Power Bypassing-Based Multiplier Design
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INTRODUCTION
Multiplication is an essential arithmetic operation in DSP
applications. For the multiplication of two unsigned n-bit
numbers, the multiplicand, A = an-1 an-2, . . . , a0, and the
multiplier, B = bn-1 bn-2, . . . , b0, the product, P = P2n-1P2n-
2, . . . , P0, can be represented as the following equation:
To achieve the high-performance demand in DSP
applications, the structure of a parallel array multiplier is
widely used and the typical implementation of such an array
multiplier is Braun design. In a nxn Braun multiplier[1], the
multiplier array consists of (n-1) rows of carry-save
adders(CSAs) and a (n-1)-bit ripple-carry adder in the last
row, in which each row contains (n-1) full adders(FAs). The
(n-1) FAs in the first CSA row that have only two valid
inputs can be replaced by (n-1) half adders(HAs).
LOW-POWER BYPASSING-BASED MULTIPLIER
DESIGNS
For a low-power row-bypassing multiplier[7], the
addition operations in the j-th row can be bypassed for the
power reduction if the bit, bj, in the multiplier is 0, i. e., all
partial products, aibj, 0 ≤ i ≤ n-1, are zero. As a result, the
addition operations in the j-th row of CSAs can be bypassed
and the outputs from the (j-1)-th row of CSAs can be
directly fed to the (j+1)-th row of CSAs without affecting
the multiplication result. In the multiplier design, each
modified FA in the CSA array is attached by three tri-state
buffers and two 2-to-1 multiplexers. Because the addition
operations of the rightmost FAs in the CSA rows are
bypassed, the extra correcting circuits must be added to
correct the final multiplication result. In Fig. 1, a 4x4 Braun
multiplier with row bypassing can be illustrated.
ANALYSIS OF HARDWARE COST IN TRANSISTORS
In all the bypassing-based multipliers, we use the 28-
transistor implementation of a full adder, FA, the 14-
transistor implementation of a half adder, HA, the 8-
transistor implementation of a XOR gate, the 6-transistor
implementation of a AND/OR gate, the 4-transistor
implementation of a NAND gate, the 4-transistor
implementation of a tri-state buffer or a 2-to-1 multiplexer
[7] and the 2-transistor implementation of the NOT gate or
an incremental adder, A+1. For an original nxn Braun
multiplier, it is clear that n2 AND gates, n half adders and
(n2-2n) full adders are used and the number of total
transistors is 34n2-42n.
CONCLUSIONS
Based on the simplification of the addition operations in a
low-power bypassing-based multiplier, we propose a twodimensional
low-cost low-power multiplier design. In the
consideration of hardware cost and power consumption, the
experimental results show that our proposed low-cost
multiplier achieves higher power reduction with lower
hardware cost than the other proposed multipliers.