08-01-2013, 11:41 AM
PERFORMANCE,IMPROVE MENTS AND LIMITATIONS OF MULTI-GATE MOSFETS
PERFORMANCE.ppt (Size: 893.5 KB / Downloads: 37)
ABSTACT
Classical scaling of CMOS is now in nanometer regime and can hardly meet the roadmap if scaled further. Different types of new Multigate architectures are becoming more and more popular for future generation nanoscale MOSFETs. In this review paper the evolution of Multigate MOSFETs and their superior performance characteristics over the bulk planar transistors has been explored. Also the fabrication challenges and other issues regarding these new kinds of devices have been summarized.
WHY MULTI-GATE MOSFETS?
For the past 40 years or so the conventional scaling or classical scaling of the bulk Silicon MOSFETs first pro- posed by Dennard was sufficient to meet the Moores law of scaling.
After the 130nm node this regular scaling failed to give the required performance goals and the industries started to add different performance boosters to meet the requirement
At below 32nm there are a whole lot of problems which cant be addressed without going for a novel device architectures like UTBSOI, Multigate FET etc.
Short Channel Effects (SCE): As the device dimensions scales into nanometer regime the junction depth of source and drain cannot be controlled very precisely. Field lines form the drain and source penetrates into the channel and the gate control decreases.
DIFFERENT MULTIGATE ARCHITECTURES
Multigate transistor can be realized both on bulk or silicon on insulator (SOI) substrates. But when bulk wafers are used isolation from one device to another becomes a dominant problem as can be understand from the structures discussed below.
the silicon body thickness can be precisely controlled in case of SOI wafers and that gives the control of junction depth and depletion region thickness. Hence the benefits of Multigate architectures are best exploited on SOI wafer.
Body SOI (UTBSOI) or other variant of SOI transistors like Partially Depleted SOI (PDSOI), Fully Depleted SOI (FDSOI), Silicon On Nothing (SON), initially begun with only one gate. These are planar technology and they are very same in all the fabrication aspects as in planar bulk CMOS.
FABRICATION ISSUES
The processing of SOI wafers with thin enough silicon layer on top is already demonstrated. Though it is costly, large scale production may bring down the cost. There are two main processes as SIMOX and BESOI for getting the SOI wafer from silicon wafer.
Fabrication of dual gate MOSFETs of type 1 can be found in [3]. These processes are very critical for large scale integration. Type II DG MOSFETs also, there are not too much future as have been discussed already.
The type III MOSFETS or FINFETs or Tri-GATE versions are being reported in large numbers now a days.
The starting substrate is a SOI wafer with a buried oxide of requires thickness. FinFETs are fabricated with fin width approximately half of the minimum gate length. Two main methods which efficiently use the best possible lithography dimension are resist defined fin patterning (RDF) and the spacer defined fin patterning (SDF).
CHALLENGES WITH MULTIGATE DEVICES
Though there are a number of miraculous advantages with the Multigate devices, there are also some serious issues still to be addressed before it can go to a large scale integration platform. These are parasitic resistance and capacitances is- sues, compatibility with high-K and metal gate technologies and strain engineering. There are also design level challenges to be addressed like compact modeling of the device
Mobility Degradation: Very thin film of fin devices may have mobility issues due to phonon scattering and also due to surface roughness due to etching technique that is used to pattern the fins.so the advantage of undoped channel mobility may be lost.
Source-Drain Series Resistnace: With very thin and high aspect ratio fins, doping the source and drain properly may be a issue and that contributes to the large sourec darin extension resistance. Also these devices have source and drain contact far from the gate. So the thin film gives additional resistance.Plasma doping of fins,epitaxial extension.schottky source and drain are some of the approaches that can reduce this resistance.