04-02-2013, 12:50 PM
VHDL Coding Exercise 4: FIR Filter
VHDL Coding.ppt (Size: 1.68 MB / Downloads: 85)
Algorithm
High-Level System Diagram
Context of the design
Inputs and Outputs
Throughput/rates
Algorithmic requirements
Algorithm Description
Mathematical Description
Performance Criteria
Accuracy
Optimization constraints
Implementation constraints
Area
Speed
RTL-Design
Choose an architecture under the following constraints:
It meets ALL timing specifications/constraints:
Throughput
Latency
It consumes the smallest possible area
It requires the least possible amount of power
Decide which additional functions are needed and how they can be implemented efficiently:
Storage of samples x(k) => MEMORY
Storage of coefficients bi => LUT
Address generators for MEMORY and LUT=> COUNTERS
Control => FSM
Translation into VHDL
Some basic rules:
Sequential processes (FlipFlops)
Only CLOCK and RESET in the sensitivity list
Logic signals are NEVER used as clock signals
Combinatorial processes
Multiple assignments to the same signal are ONLY possible within the same process => ONLY the last assignment is valid
Something must be assigned to each signal in any case OR There MUST be an ELSE for every IF statement
More rules that help to avoid problems and surprises:
Use separate signals for the PRESENT state and the NEXT state of every FlipFlop in your design.
Use variables ONLY to store intermediate results or even avoid them whenever possible in an RTL design.