10-06-2013, 02:43 PM
A PRACTICAL TRAINING REPORT ON VHDL
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VHDL DESIGN FLOW
The starting point of design process is the initial logic entry of the circuit that is to be implemented. The step typically involves drawing a schematic capture program, entering a VHDL description, or specifying Boolean expressions.
Regardless of the initial design entry, the circuit description is usually translated into a standard form such as Boolean expressions. The Boolean expressions are then processed by a logic optimization tool, which manipulate the expressions. The goal is to modify these expressions to optimize the area or speed of the final circuit .A combination of both area and delay requirements may also be considered. This optimization usually performs the equivalent of an algebraic minimization of the Boolean expressions and it is appropriate when implementing a logic circuit in any medium, not just FPGAs.
The optimized Boolean expression must next be transformed into a circuit of FPGA logic blocks. A technology-mapping program does this. The mapper may attempt to minimize the total number of blocks required, which is known as area optimization. Alternatively, the objective may be to minimize the number of stages of logic blocks in time-critical paths, which is called delay optimization.
Having mapped the circuit into logic blocks, it is necessary to decide where to place each block in the FPGA’s array. A placement program is used to solve this problem. Typical placement algorithm attempt to minimize the total length of interconnect required for the resulting placement.
The final step in the CAD system is performed by the routing software, which assigns the FPGA wire segment and chooses programmable switches to establish the required connection among the logic blocks .The routing software must ensure that 100 percent of the required connections are formed, otherwise the circuit cannot be realized in a single FPGA. Moreover it is often necessary to do the routing such that the propagation delays in time-critical connections are minimized.
INITIAL DESIGN ENTRY
As integrated circuit technology has improved to allow more and more components on a chip, digital systems have continued to grow in complexity. As digital systems have become more complex, detailed design of the systems at the gate and flop-flop level has become very tedious and time consuming. For this reason, use of hardware languages in the digital design process continues to grow importance. A hardware description language allows a digital system to be designed and debugged at a higher level before conversion to the gate and flip flop level. Use of synthesis computer aided design tools to do this conversion is becoming more widespread. This is analogous to writing software programs in high-level languages such as C and then using a compiler to convert the programs to machine language. The two most popular hardware description languages are VHDL and Verilog.
WHAT IS VHDL?
VHDL is an acronym for very high-speed integrated circuit hardware description language. It is a general-purpose hardware description language that is specifically designed to describe the organization and function of digital hardware system, circuit boards & components at many level of abstraction ranging from simple gate to complete digital electronics systems. VHDL model is a textual description of a hardware design or a piece of design that, when simulated mimics the design behavior.
HISTORY
The requirement for the language were first generated in 1980, under the Very High Speed Integrated Circuit (VHSIC) project of US government, to enhance the electronic design process, technology, and procurement, spawning development of many advanced integrated circuit process technologies. In this program, a number of US companies were involved in the design of VHSIC chip for the Department of Defense (DOD), USA. At that time, most of the companies were using different HDL to describe and developed their ICs. As a result different vender could not effectively exchange design with one another. Thus a need for a standardized HDL for the design, documentation and verification of digital system was generated. A team of three of companies, IBM, TI & INTERMETRICS, developed a version of language. In 1986, VHDL was proposed as an IEEE standard. It went through a number of revisions and changes until it was adopted as the IEEE 1076 standard in December 1987.
CAPABILITES OF VHDL
The following are the major capabilities that VHDL provide along with the feature that differentiate it from other Hardware Description languages.
1. The language can be used as an exchange medium between chip vender and CAD tool users. Different chip venders can provide VHDL description of their components to system designers. CAD tool users can use it to capture the behavior of the design at a high level of abstraction for functional simulation.
2. The language can also be used as a communication medium between different CAD and CAM tools. For example a schematic capture program may be used to generate a VHDL description for the design, which can be used as an input to a simulation program.
3. The language supports hierarchy i.e. a digital system can be modeled as a set of interconnected sub-components.
ADVANTAGES OF VHDL OVER PROCEDURAL LANGUAGES
Main difference between VHDL and other programming languages like C/C++ are
a) VHDL is a parallel language, while C/C++ are sequential languages. Each statement occurring in VHDL is executed concurrently, while in C/C++ each statement is executed sequentially and at its own turn. In VHDL explicit constructs exist for explicit sequential steps.
b) VHDL is a strongly typed language. It doesn’t allow any mismatching of types, though type conversion is permitted.
c) VHDL allows use of explicit time delay, which isn’t applicable in procedural languages. In procedural languages the right hand side value is assigned to the left hand side value as soon as the statement is executed. In VHDL there is an advantage that the computed value can be assigned to a signal after any time delay.
d) VHDL model cannot be implemented in real time application directly like other procedural languages. It is simulated and synthesized using in built system clock.
THE VHDL DESIGN HIERARCHY
Any hardware design can be described in terms of its operation at different levels of abstraction, from system through to logic gate. At each level of this hierarchy the overall inputs and outputs remain the same but the functionality of distinct sections become clearer. When the local inputs and outputs and the function of a block are sufficiently defined, the hardware can be designed.
VHDL is capable of describing a well-defined hardware block at any level of abstraction. A design entity is the VHDL representation of such a block and can be considered to be at the top of the design hierarchy. Within the design entity, the function of the hardware is often further decomposed by using external and internal blocks.
ADVANTAGES OF VHDL OVER PROCEDURAL LANGUAGES
Main difference between VHDL and other programming languages like C/C++ are
a) VHDL is a parallel language, while C/C++ are sequential languages. Each statement occurring in VHDL is executed concurrently, while in C/C++ each statement is executed sequentially and at its own turn. In VHDL explicit constructs exist for explicit sequential steps.
b) VHDL is a strongly typed language. It doesn’t allow any mismatching of types, though type conversion is permitted.
c) VHDL allows use of explicit time delay, which isn’t applicable in procedural languages. In procedural languages the right hand side value is assigned to the left hand side value as soon as the statement is executed. In VHDL there is an advantage that the computed value can be assigned to a signal after any time delay.
d) VHDL model cannot be implemented in real time application directly like other procedural languages. It is simulated and synthesized using in built system clock.
THE VHDL DESIGN HIERARCHY
Any hardware design can be described in terms of its operation at different levels of abstraction, from system through to logic gate. At each level of this hierarchy the overall inputs and outputs remain the same but the functionality of distinct sections become clearer. When the local inputs and outputs and the function of a block are sufficiently defined, the hardware can be designed.
VHDL is capable of describing a well-defined hardware block at any level of abstraction. A design entity is the VHDL representation of such a block and can be considered to be at the top of the design hierarchy. Within the design entity, the function of the hardware is often further decomposed by using external and internal blocks.
ENTITY DECLARATION
The entity declaration is the interface between the external environment, such as a top-level schematic, and the design. It is at the top of the design three for every external block. Hence, it will usually contain a description of the inputs to and outputs from the block in the form of a port statement. An entity declaration without a port statement does not have any external connections.
The Generic statement can be used within the entity declaration to pass timing, control or environmental data into the design unit. A component declaration may also have a Generic statement. This information is useful when simulating a design, but when synthesizing most of it is irrelevant. Hence, the Generic statement usually only supports the declaration of integer generics, which have a constant value and can therefore be substituted into the associated design unit at compile time.
ARCHITECTURE BODY
The architecture body is used to specify the relationship between the inputs and outputs declared in the entity. It therefore describes the actual function of the hardware. Although each entity must be unique, several architectures can be associated with one entity. This allows the function of a block to the changed without changing its external structure.
The architecture body contains any number of concurrent statements components and internal blocks are also of this type. These statements can be considered to be executing asynchronously and completely independently of each other. It is therefore crucial to understand how the relationships between different concurrent statements are going to affect not only the behavior but also the logical structure of the hardware that synthesis will produce.
Additionally, certain concurrent statements may contain a number of sequentially executing statements. Such flexibility allows the architecture body to be constructed using three possible language styles. Choosing a particular approach does not limit the design to that one style. In fact, many functional descriptions can be implemented in more than one style. In general, a combination of two or all three styles is often required to obtain the most compact and clear VHDL code.
Dataflow style
Dataflow style architecture models the hardware in terms of the movement of data Over continuous time between combinational logic components such as adders, decoders and primitive logic gates. It describes the register-transfer level behavior of a circuit. The language topics that are most relevant to the dataflow style of architecture include the following:
Operators-logical, relational and mathematical;
Operator overloading;
Concurrent assignment statements.
This style is not appropriate for the modeling of sequential logic. Instead, and as its name suggests, it is best applied in the modeling of data driven elements such as an arithmetic logic unit (ALU)
behavioral style
The behavioral style architecture contains concurrent statements with sections of sequential statements that describe the outputs of the circuit at a discrete moment in time given particular inputs. While similar language constructs are often found in dataflow and behavioral style architectures, only the latter explicitly exhibit the notions of time and control. This style describes the function of the circuit at the algorithmic level.