12-04-2014, 02:59 PM
Logic Built in Self Test
Logic Built .ppt (Size: 222.5 KB / Downloads: 11)
Verification Vs Testing
Verification
Design errors
Testing
Manufacturing defects
Aging defects
In-field regular testing is required
Fault models and Detection
Gate level Stuck-at Fault model
Transistor level Stuck-at Fault model
Bridging Fault Model
Delay faults
Testing Problem at Deep Sub-Micron
Decreasing feature size
Low power supply
Increasing Number of pins
Test equipment cost
More test vectors
Increasing gate count
Memories, RF, MEMS on the chip
Different test methodologies
Scan Design Techniques
Flip-flop of design Scan registers
Use of Multiplexer
Increased controllability and observability
Two step synthesis approach: scan mode and scan chain connection are done at second step
Special scan registers
Boundary Scan
Use reduced number of pins
Less cost of tester
Need scannble latches at non-test I/O
Additional cost of Mux (Performance)
Large handling capabilities of ATPG system required
Traditional LBIST architecture- STUMPS
Self-testing using MISR and parallel shift (Stumps)
PRPG generate input for internal scan chains
Compress the response in MISR
Linear Feedback Shift Register (LFSR) generate pseudo random pattern.
Synthesis stages
Data-flow Scheduling for Testability
Binding for Testability
Test concurrency matrix
Test Register Selection
Incremental approach
Test Path Definition
Test point insertion
Test Scheduling
Conclusion
At deep submicron test cost and test time are major issues to be considers
BIST can be a good option in this scenario
To ensure good test performance, it is necessary to estimate the quality of test behavior during synthesis.