22-08-2012, 02:40 PM
Performance Analysis of Carbon Nanotube Interconnects for VLSI Applications
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Abstract
The work in this paper analyses the applicability of carbon
nanotube (CNT) bundles as interconnects for VLSI circuits, while
taking into account the practical limitations in this technology. A
model is developed to calculate equivalent circuit parameters for
a CNT-bundle interconnect based on interconnect geometry. Using
this model, the performance of CNT-bundle interconnects (at
local, intermediate and global levels) is compared to copper
wires of the future. It is shown that CNT bundles can outperform
copper for long intermediate and global interconnects, and can
be engineered to compete with copper for local level interconnects.
The technological requirements necessary to make CNT
bundles viable as future interconnects are also laid out.
Introduction
The resistance of copper interconnects, with cross-sectional
dimensions of the order of the mean free path of electrons (~40
nm in Cu at room temperature) in current and imminent technologies
[1], is increasing rapidly under the combined effects of enhanced
grain boundary scattering, surface scattering and the presence
of the highly resistive diffusion barrier layer [2]. The steep
rise in parasitic resistance of copper interconnects poses serious
challenges for interconnect delay [1] (especially at the global level
where wires traverse long distances) and for interconnect reliability
[3], hence it has a significant impact on the performance and
reliability of VLSI circuits.
Background and Previous Work
Resistivity Increase in Cu Interconnects
The resistivity of wires with dimensions in the range of, or
less than, the mean free path of metal (copper: 40 nm at room
temperature) has been modeled and experimentally verified on
sub-100 nm copper wires [2]. The resistivity model is based on
the Fuchs-Sondheimer model for surface scattering of electrons
(Eq. 1) and the theory of Mayadas and Shatzkes for the scattering
of electrons at grain boundaries (Eqs. 2 and 3) [2]. Here ρ
0 is
resistivity of the bulk material, p is the fraction of electrons scattered
specularly at the surface, d is width of the wire, l is mean
free path, R is the reflectivity coefficient that denotes the fraction
of electrons that are not scattered by the potential barrier at a grain
boundary, and d' is the average distance between grain boundaries.
Previous Work on Performance of CNT Interconnects
Over the past year, several attempts have been made at
evaluating the prospects of CNT-bundle interconnects vis-à-vis
copper interconnects of the future. In [3] it is shown that while
carbon nanotube interconnects can alleviate the severe reliability
limitations of future copper interconnects, high density CNT bundles
are needed in order to achieve performance comparable to
copper. The work in [29] compares the performance of an isolated
CNT and a flat array of CNTs (see Fig. 6) behaving as interconnections
and reports that CNT interconnects do not compare favorably
with copper conductors. It is in fact trivial to see that such
configurations cannot be compared to copper interconnects due to
the intrinsically high resistance associated with an isolated CNT,
hence technologists have always focused on CNT bundles in practice
[4, 5]. The coupling capacitance model for CNT interconnects
in [29] considers only the coupling between adjacent CNTs and
not that between bundles forming adjacent interconnects (coupling
between adjacent interconnects is considered for copper
interconnects, using a simplistic parallel plate capacitance). Evidently
the coupling capacitance between adjacent CNTs forming
the same bundle will always be very high due to their physical
proximity. However, this capacitance does not appear as a load
when the CNTs form part of the same interconnection (discussed
in further detail in Section 3.2). These shortcomings lead to the
(incorrect) conclusion in [29] that carbon nanotube interconnects
are not suitable for VLSI applications.
Capacitance of a CNT-bundle
The electrostatic capacitance of a CNT bundle has not been
the subject of much analysis in the existing literature. The work in
[32] studies the electrostatic capacitive coupling to the gate electrode
for a flat array of CNT FETs.
For the electrostatic analysis of a CNT bundle, each CNT is
treated as a classical metal with equal potential over the tube,
similar to the approach in [32]. The expression for the intrinsic
plate capacitance for an isolated CNT (CE) has been shown before
(Equation 6). Fig. 7(a) schematically shows the electrostatic field
lines emanating from an isolated CNT in this case. Fig. 7(b)
shows the corresponding situation for a CNT at the bottom edge
of an interconnect bundle which is surrounded by four other
CNTs.
Summary
The applicability of carbon nanotube bundles as interconnects
of the future has been analyzed while taking into account the
practical limitations of this emerging technology. The performance
of CNT-bundle interconnects has been compared to that of
copper interconnects of future technology generations and their
applicability at different metal tiers in a VLSI design is studied.
At the local interconnect level, CNT-bundles with imperfect contacts
do not give much performance improvement. It is also shown
that there exists an optimal density less than the maximum packing
density of CNT bundles at which the interconnect propagation
delay is minimum. This is a useful finding in light of the fact that
CNT-bundles fabricated till date do not have a very high density
of CNTs [3] and all the CNTs in a bundle may not have metallic
nature. Although this fact can be advantageous to the use of CNTs
as interconnects, with technology scaling, it becomes imperative
to also reduce the additional resistance associated with imperfect
metal-nanotube contacts. In the case of long intermediate and
global interconnects, densely packed CNT bundle interconnects
show significant improvement in performance as compared to
copper interconnects.