27-08-2012, 09:57 AM
Electronic Jam
Electronic Jam.pdf (Size: 65.91 KB / Downloads: 83)
This jam circuit can be used in
quiz contests wherein any participant
who presses his button
(switch) before the other contestants,
gets the first chance to answer a question.
The circuit given here permits up
to eight contestants with each one allotted
a distinct number (1 to 8). The
display will show the number of the contestant
pressing his button before the
others. Simultaneously, a buzzer will
also sound. Both, the display as well as
the buzzer have to be reset manually
using a common reset switch.
Initially, when reset switch S9 is momentarily
pressed and released, all outputs
of 74LS373 (IC1) transparent latch
go ‘high’ since all the input data lines
are returned to Vcc via resistors R1
through R8. All eight outputs of IC1
are connected to inputs of priority encoder
74LS147 (IC2) as well as 8-input
NAND gate 74LS30 (IC3). The output
of IC3 thus becomes logic 0 which, after
inversion by NAND gate N2, is applied
to latch-enable pin 11 of IC1. With all
input pins of IC2 being logic 1, its BCD
output is 0000, which is applied to 7-
segment decoder/driver 74LS47 (IC6) after
inversion by hex inverter gates inside
74LS04 (IC5). Thus, on reset the
display shows 0.
![Adobe Acrobat PDF .pdf](https://seminarproject.net/images/attachtypes/pdf.gif)
This jam circuit can be used in
quiz contests wherein any participant
who presses his button
(switch) before the other contestants,
gets the first chance to answer a question.
The circuit given here permits up
to eight contestants with each one allotted
a distinct number (1 to 8). The
display will show the number of the contestant
pressing his button before the
others. Simultaneously, a buzzer will
also sound. Both, the display as well as
the buzzer have to be reset manually
using a common reset switch.
Initially, when reset switch S9 is momentarily
pressed and released, all outputs
of 74LS373 (IC1) transparent latch
go ‘high’ since all the input data lines
are returned to Vcc via resistors R1
through R8. All eight outputs of IC1
are connected to inputs of priority encoder
74LS147 (IC2) as well as 8-input
NAND gate 74LS30 (IC3). The output
of IC3 thus becomes logic 0 which, after
inversion by NAND gate N2, is applied
to latch-enable pin 11 of IC1. With all
input pins of IC2 being logic 1, its BCD
output is 0000, which is applied to 7-
segment decoder/driver 74LS47 (IC6) after
inversion by hex inverter gates inside
74LS04 (IC5). Thus, on reset the
display shows 0.