10-10-2012, 10:32 AM
IR Transmitter and Receiver
IR Transmitter.docx (Size: 1.27 MB / Downloads: 49)
INTRODUCTION
The distance meter commonly used as obstacle detector, this consists of IR transmitter and receiver. The signals transmitted by IR transmitter are received by receiver and supplied to the ADC Module. ADC module converts analog signals (input signals) to digital form. Its output is used in digital form (high & low logic) by employing a comparator. It uses the sensor’s output in its original analog form. Thus, along with detecting an obstacle, its exact distance can also be obtained. This is achieved by processing the output of IR sensor through an ADC0804 (analog to digital converter). The ADC is calibrated to get almost accurate distance measurement. The measured distance is also displayed on an LCD screen. The ADC0804 and LCD are interfaced with 8051 microcontroller (AT89C51) to perform these operations. The major drawback of IR based sensors is their capability of detecting short distances.
PRINCIPLE
In this project IR transmitter transmit’s the IR waves which reflected back from the obstacles. Since frequency=velocity/wavelength so velocity is calculated.The time required by the wave is calculated by the sensor. Distance=velocity*time.
IR SENSOR
The IR receiver detects the IR radiations transmitted by an IR LED. The output voltage level of this IR sensor depends upon the intensity of IR rays received by the receiver. The intensity, in turn, depends on the distance between the sensor module and the obstacle. When the distance between IR pair and obstacle is lesser, more IR radiations fall on the receiver, and vice versa. The receiver along with a resistor forms a voltage divider whose output is supplied as the input for ADC0804. Now ADC module converts this analog input to digital output.
LCD UNIT
Liquid Crystal Displays (LCDs) are categorized as none missive display devices, in that respect, they do not produce any form of light like a Cathode Ray Tube (CRT). LCDs either pass or block light that is reflected from an external light source or provided by a back/side lighting system. There are two modes of operation for LCDs during the absence of an electric field (applied Power); a mode describes the transmittance state of the liquid crystal elements. Normal White mode: the display is white or clear and allows light to pass through and Normal Black Mode: the display is dark and all light is diffused. Virtually all displays in production for PC/Workstation use are normal white mode to optimize contrast and speed.
8051 MICROCONTROLLER
AT89C51
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The devices manufactured using Atmel’s high-density nonvolatile memory technology and are compatible with the industry-standard MCS-51 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.
DESCRIPTION
The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 and 80C52 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.
OSCILLATOR CHARACTERS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.
IDLE MODE
In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
PROGRAMMING THE FLASH
The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The AT89C51 code memory array is programmed byte-by byte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.
INTERRUPT REGISTERS
The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register r. specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV @R0, #data stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.
TIMER 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.
Program Memory
After reset, the CPU begins execution from location 0000H. Each interrupt is assigned a fixed location in program memory. The interrupt causes the CPU to jump to that location, where it executes the service routine. External Interrupt 0, for example, is assigned to location 0003H. If External Interrupt 0 is used, its service routine must begin at location 0003H. If the interrupt is not used, its service location is available as general purpose program memory. The interrupt service locations are spaced at 8-byte intervals.0003H for External Interrupt 0, 000BH for Timer 0, 0013H for External Interrupt 1, 001BH for Timer 1, and so on. If an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8-byte interval. Longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use. The lowest addresses of program memory can be either in the on-chip Flash or in an external memory. To make this selection, strap the External Access (EA) pin to either VCC or GND. For example, in the AT89C51 with 4K bytes of on-chip Flash, if the EA pin is strapped to VCC, program fetches to addresses 0000H through 0FFFH are directed to the internal Flash. Program fetches to addresses 1000H through FFH are directed to external memory. In the AT89C52 (8K bytes Flash), EA = VCC selects addresses 0000H through 1FFFH to be internal and addresses 2000H through FFH to be external. If the EA pin is strapped to GND, all program fetches are directed to external memory. The read strobe to external memory, PSEN, is used for all external program fetches. Internal program fetches do not activate PSEN.
IR Transmitter.docx (Size: 1.27 MB / Downloads: 49)
INTRODUCTION
The distance meter commonly used as obstacle detector, this consists of IR transmitter and receiver. The signals transmitted by IR transmitter are received by receiver and supplied to the ADC Module. ADC module converts analog signals (input signals) to digital form. Its output is used in digital form (high & low logic) by employing a comparator. It uses the sensor’s output in its original analog form. Thus, along with detecting an obstacle, its exact distance can also be obtained. This is achieved by processing the output of IR sensor through an ADC0804 (analog to digital converter). The ADC is calibrated to get almost accurate distance measurement. The measured distance is also displayed on an LCD screen. The ADC0804 and LCD are interfaced with 8051 microcontroller (AT89C51) to perform these operations. The major drawback of IR based sensors is their capability of detecting short distances.
PRINCIPLE
In this project IR transmitter transmit’s the IR waves which reflected back from the obstacles. Since frequency=velocity/wavelength so velocity is calculated.The time required by the wave is calculated by the sensor. Distance=velocity*time.
IR SENSOR
The IR receiver detects the IR radiations transmitted by an IR LED. The output voltage level of this IR sensor depends upon the intensity of IR rays received by the receiver. The intensity, in turn, depends on the distance between the sensor module and the obstacle. When the distance between IR pair and obstacle is lesser, more IR radiations fall on the receiver, and vice versa. The receiver along with a resistor forms a voltage divider whose output is supplied as the input for ADC0804. Now ADC module converts this analog input to digital output.
LCD UNIT
Liquid Crystal Displays (LCDs) are categorized as none missive display devices, in that respect, they do not produce any form of light like a Cathode Ray Tube (CRT). LCDs either pass or block light that is reflected from an external light source or provided by a back/side lighting system. There are two modes of operation for LCDs during the absence of an electric field (applied Power); a mode describes the transmittance state of the liquid crystal elements. Normal White mode: the display is white or clear and allows light to pass through and Normal Black Mode: the display is dark and all light is diffused. Virtually all displays in production for PC/Workstation use are normal white mode to optimize contrast and speed.
8051 MICROCONTROLLER
AT89C51
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The devices manufactured using Atmel’s high-density nonvolatile memory technology and are compatible with the industry-standard MCS-51 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.
DESCRIPTION
The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 and 80C52 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.
OSCILLATOR CHARACTERS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.
IDLE MODE
In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
PROGRAMMING THE FLASH
The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The AT89C51 code memory array is programmed byte-by byte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.
INTERRUPT REGISTERS
The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register r. specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV @R0, #data stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.
TIMER 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.
Program Memory
After reset, the CPU begins execution from location 0000H. Each interrupt is assigned a fixed location in program memory. The interrupt causes the CPU to jump to that location, where it executes the service routine. External Interrupt 0, for example, is assigned to location 0003H. If External Interrupt 0 is used, its service routine must begin at location 0003H. If the interrupt is not used, its service location is available as general purpose program memory. The interrupt service locations are spaced at 8-byte intervals.0003H for External Interrupt 0, 000BH for Timer 0, 0013H for External Interrupt 1, 001BH for Timer 1, and so on. If an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8-byte interval. Longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use. The lowest addresses of program memory can be either in the on-chip Flash or in an external memory. To make this selection, strap the External Access (EA) pin to either VCC or GND. For example, in the AT89C51 with 4K bytes of on-chip Flash, if the EA pin is strapped to VCC, program fetches to addresses 0000H through 0FFFH are directed to the internal Flash. Program fetches to addresses 1000H through FFH are directed to external memory. In the AT89C52 (8K bytes Flash), EA = VCC selects addresses 0000H through 1FFFH to be internal and addresses 2000H through FFH to be external. If the EA pin is strapped to GND, all program fetches are directed to external memory. The read strobe to external memory, PSEN, is used for all external program fetches. Internal program fetches do not activate PSEN.