15-11-2012, 06:05 PM
CLOCK DISTRIBUTION
CLOCK DISTRIBUTION.pptx (Size: 278.66 KB / Downloads: 30)
INTRODUCTION
A clk signal must be distributed to all clocked storage elements with minimum of skew and jitter.
Variations in wire and driver delays,a non uniform and time varying clock load and noise-uncertainty of clk.
Off –chip and On-chip clk distribution.
Off-chip clock distributon
Off-chip wire and cables have ideal delays and their distribution is easy problem.
By trimming wire length and matching buffer delays or using standing waves-global clk distributed.
Constraints in operating frequency and increased sensitivity to timing noise.
System divided into small clk domains
Clock Distribution Trees
High performance clk distribution using differential signalling.
Multiple clock loads on a line introduce skew and impedance discontinuity.So lines series or parallel terminated.
Fan out driver distribute signal to a no: of output drivers
To reduce skew build fan out driver using zero delay drivers
Phase-Locked Clock DistributionNetworks
Clock trees vulnerable to no: of single point failures.
Use phase locked network of clock oscillators
Each board –its own VCXO clk oscillator and local clk distribution tree.
Adjacent modules exchange clocks via cables.
Two phase comparators used to compare modules clk to 2 neighbours.
Outputs summed to control VCXO.
If one module fails rest of system continues in phase lock.
With VCXO at center frequency one module run independently.
Round-Trip Distribution
Clk signal send along a transmission line across set of modules and back again across the same set of modules in reverse order.
If lines matched ,average time of arrival of each edge of Fclk and reverse Rclk clock is same at every pt on line.
Here each module in the system synchronize with 2 clocks
Jitter in On-Chip Clock Distribution
Due to power supply variations
Differential and common mode power supply cause clock jitter.
Differential power supply noise modulates the delay of clk drivers.
Clock to clock variation in IR drops and LC oscillations cause jitter.
Reduced by buiding clk drivers insensitive to supply variations.