22-12-2012, 06:00 PM
AREA OPTIMIZED ARCHITECTURE AND VLSI IMPLEMENTATION OF RC5 ENCRYPTION ALGORITHM
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ABSTRACT
The rapidly growth of the amount of the transmitted data
over wireless networks, has triggered special needs for
security. Today, wireless communications protocols have
dedicated layers to ensure security in the transmission
channel. Wireless Transport Layer Security (WTLS) is
widely used in both Wireless Application Protocol and
Open Mobile Alliance. Privacy in WTLS is based on the
RC5 cipher. In this paper, an area optimized architecture
and an FPGA implementation for RC5 is introduced. The
proposed implementation allocates less area resources,
with a range between 28 to 33%, compared with the
conventional architecture. The proposed architecture has
been designed with pipeline technique, which achieves
high speed performance. Finally, the proposed RC5
implementation is proved superior to other related works,
compared in both frequency and throughput.
INTRODUCTION
The ultimate success of wireless communications
depends on public confidence in the security and
confidentially of the transactions involved. Encryption
algorithms play an essential role in achieving both these
aims. Modern cryptography employs a combination of
symmetric encryption algorithms and public key
algorithms. Asymmetric (public key) algorithms have
been proved dramatically slow to support bulk data
encryption. The encryption performance of
communication systems is critically dependent on the
performance of symmetric algorithms. The most famous
and widely used block ciphers of this kind are: AES,
DES, RC5 and IDEA.
RC5 [1] is widely used in communications world, in
order to ensure security with high level strength for bulk
encryption. Especially it is used in Wireless Transport
Layer Security (WTLS) [2]. WTLS is the security layer
for both Wireless Application Protocol [3] and Open
Mobile Alliance (OMA) [4]. WAP is a result of the WAP
Forum’s efforts to promote industry-wide specifications
for technology useful in applications and services that
operate over wireless communication networks.
SYSTEM ARCHITECTURE
The implementation of RC5 demands a set of
parameters that have to be specified like key rounds,
operation word-lengths and secret key variables, before
RC5 starts to operate. It is no intended that RC5 is secure
for all possible values of the above specified parameters.
If RC5 was configured with the most secure parameters
values, the performance of many applications would be
minimized in no acceptable levels [6]. In some cases,
where the security is the only main request,
implementation performance is not a high level
importance issue. All the choices of the parameters seem
to be available and usable in theory, but many of them in
practice may be forbidden [6].
Conventional RC5 Architecture
The conventional architecture for RC5_Core
implementation is illustrated in Fig. 2. It performs both
encryption and decryption with two different cores,
Encrypt and Decrypt, respectively. This architecture
design is based on RC5 specifications, which define two
different schemes: one for encryption and one for
decryption. The Initial Unit divides the input message
into two 32-bit words (A and B). Especially in the case of
encryption operation, modulo additions are performed
between the first two keys S(0), S(1) and the words A and
B, respectively. Core_Encrypt performs the encryption
transformation of 12 rounds. In every round i, two proper
keys S(2i), S(2i+1) are used. In order to accomplish the
three primitive encryption operations which are described
in Section 2, Core_Encrypt uses a modulo adder 232, a
left circular shift register and a XOR block (Fig. 3a).
Respectively the Core Decrypt performs the decryption
scheme.
SUMMARY
In this paper an area optimized architecture is proposed,
for the implementation of RC5 encryption algorithm. The
proposed implementation is compared with the
conventional one, and it is proven that with the proposed
design a good reduction to the area resources is achieved.
Especially the proposed architecture minimizes the
covered area resources with a range between 28 to 33%,
for the FPGA implementation. In addition the proposed
architecture is superior to the conventional in the Area-
Delay Product, but it is a little bit slower in operating
frequency. Comparisons with other related published
works, prove that the proposed architecture is better in
operating frequency and throughput.