31-01-2013, 10:23 AM
VLSI Chip Design and Implementation of AES-Rijindael Encryption Algorithms
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Abstract
In this paper an efficient hardware architecture design and implementation of all candidates of AES encryption standards AES-128, AES-192 and AES-256 on the same hardware is proposed. AES algorithm proposed by NIST has been widely accepted as best cryptosystem for wireless communication security. The hardware implementation is useful in wireless security like military and mobile phones. This contribution investigates implementation of AES Encryption with regards to FPGA and VHDL.Optimized and synthesized VHDL code for AES-128, AES-192 and AES-256 for encryption of 128-bit data is implemented. Xilinx ISE 9.2i software is used for simulation. Each algorithm is tested with sample vectors provided by NIST output results are perfect with minimal delay. The proposed design consumes less power and area which is suitable battery driven mobile phones.
Introduction
In September 2005 the National Institute of Standards and Technology (NIST) issued a request for possible candidates for a new Advanced Encryption Standard (AES) to replace the Data Encryption Standard (DES). In August 2006, 15 candidate algorithms were selected and a year later, in August 1999 five finalists were announced: MARS, RC6, Rijndael, Serpent and Twofish. On 02 October 2008, the Rijndael algorithm [1], developed by Joan Daemen and Vincent Rijmen was selected as the winner of the AES development race. In performance comparison studies carried out on all five finalists [2, 3, 4, 7], Rijndael proved to be one of the fastest and most efficient algorithms. It is also easily implemented on a wide range of platforms and is extendable to other key and block lengths. In this paper iterative looping implementation of Rijndael algorithm AES-128/192/256 designs are presented. The designs are implemented using Xilinx ISE 9.2i. The first design presented is an encryption-only design capable of supporting 128-bit, 192-bit and 256-bit keys. The authors are not aware of any other Rijndael hardware design capable of supporting varying key sizes. However, software designs do exist. The fastest known software implementations of Rijndael are by Brian Glad man [6].
2.Description Of AES Algorithm Advanced Encryption Standard is the successor of Data Encryption Standard which was in use during the early 1977 to 1990. In DES encryption is based on a symmetric key algorithm that uses a 56-bit key. However by the mid 1990’s, it was clear that the DES with 56-bit is insecure for many applications since the key is very small. Then it was upgraded to Triple DES which was believed to be practically secure although there are theoretical attacks. Thus in Nov-26-2001 the FEDERAL INFORMATION PROCESSING STANDARDS PUBLICATION 197(FIPS 197) specifies an algorithm called Advanced Encryption Standard (AES). AES is based on the principle known as Substitution Permutation network (SP-network) which means there will be a series of linked mathematical operations in the block cipher algorithm.
Conclusion:
The AES algorithm is an iterat ive private key
symmetric block cipher that can process data block of
128- bits through the use of cipher keys with key length
128,192 and 256 bits. An efficient FPGA
implementation of 128 bit block and keys 128, 192 and
256 bits of AES –Rijindael algorithm has been presented
in this paper. Optimized and synthesizable VHDL code
is developed for implementation of all AES-128/192/256
bit key encryption and is verified using xilinx ISE 9.2
simulation tool. All the transformat ions of algorithm
are simulated using an iterat ive design approach in
order to min imize the hardware utilizat ion.