01-04-2010, 09:41 PM
Seminar On Crusoe processor
Presented BY:
Name : p.veera chamy
Roll no : APN 09
Class :I MSCCS&IT
INTRODUCTION :
Mobile computing has been the buzzword for quite a long time. Mobile computing devices like laptops, notebook PCs etc are becoming common nowadays. The heart of every PC whether a desktop or mobile PC is the microprocessor. Several microprocessors are available in the market for desktop PCs from companies like Intel, AMD, Cyrix etc.
The mobile computing market has never had a microprocessor specifically designed for it. The microprocessors used in mobile PCs are optimized versions of the desktop PC microprocessor.
Mobile computing makes very different demands on processors than desktop computing. Those desktop PC processors consume lots of power, and they get very hot. run through the airport. . The market will still reject a newly designed microprocessor with low power consumption if the performance is poor. So any attempt in this regard must have a proper 'performance-power' balance to ensure commercial success
Crusoe is the new microprocessor, which has been designed specially for the mobile computing market .It has been, designed after considering the above-mentioned constraints. A small Silicon Valley startup company called Transmeta Corp developed this microprocessor.
The concept of Crusoe is well understood from the simple sketch of the processor architecture, called 'amoebaâ„¢. i.e. it has a software part and a hardware part with the software layer surrounding the hardware unit.
The role of software is to act as an emulator to translate x86 binaries into native code at run time. Crusoe is a 128-bit microprocessor fabricated using the CMOS process. The chip's design is based on a technique called VLIW to ensure design simplicity and high performance.
The other two technologies using are Code Morphing Software and LongRun Power Management. The crusoe hardware can be changed radically without affecting legacy x86 software.
CRUSOE PROCESSOR VLIW HARDWARE
VLIW stands for Very Long Instruction Word. VLIW is a method that combines multiple standard instructions into one long instruction word. This word contains instns that can be executed at the same time on separate chips or different parts of the same chip. It provides explicit parallelism, i.e. executing more than one basic (primitive) instn at a time.
Trace scheduling is an important technique in VLIW processing. i.e. the compiler processes the code and determines which path is the most frequently traveled, and then optimizes this path. Basic blocks that compose the path are separated from the other basic blocks. The path is then optimized and rejoined with the other basic blocks using split and rejoin blocks.
Basic principles of VLIW Architecture
Dynamic scheduling is another important method when compiling VLIW code. The process called split-issue splits the code into two phases,
¢ This allows for multiple instns, instns having certain delays etc to execute at the same time. H/W support is needed to implement and needs delay buffers and temporary variable space (TVS) in the h/w.
¢ The TVS is needed to store results when they come in. The results computed in phase two are stored in temporary variables and are loaded into the appropriate phase one register when they are needed.
VLIW has been described as a natural successor to RISC, whose instn set consists of simple instructions (RISC-like). because it moves complexity from the hardware to the compiler, allowing simpler, faster processors. One objective of VLIW is to eliminate the complicated instruction scheduling. The compiler must assemble many primitive operations into a single "instruction word" such that the multiple functional units are kept busy.
Crusoe VLIW in Microprocessor
With the Code Morphing software handling x86 compatibility, Transmeta hardware designers created a very simple, high-performance, VLIW engine with two integer units,
¢ floating-point unit
¢ memory (load/store) unit
¢ branch unit.
¢ A Crusoe processor long instruction word, called a molecule, can be 64 bits or 128 bits long and contain up to four RISC-like nstructions,called atoms. All atoms within a molecule are executed in parallel, and the molecule format directly determines how atoms get routed to functional units; this greatly simplifies the decode and dispatch hardware
CRUSOE PROCESSOR ARCHITECTURE
The Crusoe microprocessor is available in the market in the following versions:
¢ TM3120
¢ TM3200
¢ TM5400
¢ TM5600.
¢ The basic architecture of all the above models are same except for some minor changes since various models have been introduced for different segments of the mobile computing market.
¢ The Crusoe Processor incorporates integer and floating point execution units, separate instruction and data caches, a level-2 write-back cache, memory management unit, and multimedia instructions. In addition to these traditional processor features, there are some additional units, which are usually part of the core system logic that surrounds the microprocessor.
¢ The VLIW processor, in combination with Code Morphing software and the additional system core logic units, allow the Crusoe Processor to provide a highly integrated, ultra-low power, high performance platform solution for the x 86 mobile markets.
Processor Core
The Crusoe Processor core architecture is relatively simple by conventional standards. It is based on a VLIW 128-bit instn set. Within this VLIW architecture, the control logic of the processor is kept very simple and s/w is used to control the scheduling of instns.
This allows a simplified and very straightforward h/w implementation with an in-order 7-stage integer pipeline and a 10-stage floating-point.
This cache architecture assures maximum internal memory bandwidth for performance intensive mobile applications, while maintaining the same low-power implementation that provides a superior performance-to-power consumption ratio relative to previous x86 implementations.
Execution h/w for logical, arithmetic, shift, and floating point instns, as in conventional processors, the Crusoe has very distinctive features from traditional x86 designs
Integrated DDR SDRAM Memory Controller
¢ DDR SDRAM interface is the highest performance memory interface available on the Crusoe. The DDR SDRAM controller supports only Double Data Rate (DDR) SDRAM and transfers data at a rate that is twice the clock frequency of the inter-face.
Integrated SDR SDRAM Memory Controller
¢ The SDR SDRAM memory controller supports up to four banks, equivalent to two Small Outline Dual In-line Memory Modules (SO-DIMMS), of Single Data Rate (SDR) SDRAM that can be configured as 64-bit or 72-bit
¢ .These SO-DIMMs can be populated with 64M-bit, 128M-bit or 256M-bit devices.
¢ All SO-DIMMs must use the same frequency SDRAMs, but there are no restrictions on mixing different SO- DIMM configurations into each SO-DIMM slot.
¢ The frequency setting for the SDR SDRAM interface is initialized during the power-on boot sequence.
Integrated PCI Controller
¢ The Crusoe Processor includes a PCI bus controller that is PCI 2.1 compliant.
¢ The PCI bus is 32 bits wide, operates at 33 MHz, and is compatible with 3.3V signal levels.
¢ It is not 5V tolerant, however. The PCI controller on provides a PCI host bridge, the PCI bus arbiter, and a DMA controller.
Serial ROM Interface
¢ The Crusoe serial ROM interface is a five-pin interface used to read data from a serial flash ROM.
¢ The flash ROM is 1M-byte in size and provides non-volatile storage for the CMS.
¢ During the boot process, the Code Morphing code is copied from the ROM to the Code Morphing memory space in SDRAM. Once trans-erred, the Code Morphing code requires 8 to 16M-bytes of memory space.
¢ The portion of SDRAM space reserved for CMS is not visible to x86 code.
¢ This interface may also be used for in-system reprogramming of the flash ROM
FEATURES OF VARIOUS CRUSOE PROCESSORS
¢ VLIW processor and x86 Code Morphing software provide x86 compatible mobile platform solution.
¢ Processor core operates at 366 and 400 MHz.
¢ PCI (Peripheral Component Interface) bus controller
with 33 MHz, 3.3V interface
¢ Advanced power management features and very-low power operation
extend mobile battery life
¢ Full System Management Mode (SMM) support
¢ Compact 474-pin ceramic BGA (Ball Grid Array) package
¢ LongRun advanced power management with ultra-low power operation
Application:
¢ Prototype web based application
¢ Crusoe Special Embedded (SE) processors
¢ A processor that executes every instruction one after the other may use processor resources inefficiently, potentially leading to poor performance.
¢ The performance can be improved by executing different sub-steps of sequential instructions simultaneously or even executing multiple instructions entirely
¢ Crusoe processor support Symbian Os software.
Contents :
1. Introduction
2. CRUSOE PROCESSOR
VLIW HARDWARE
3. Crusoe VLIW in Microprocessor
4. Processor Core
5. SDRAM Memory Controller
6. Features
7. Application
Presented BY:
Name : p.veera chamy
Roll no : APN 09
Class :I MSCCS&IT
INTRODUCTION :
Mobile computing has been the buzzword for quite a long time. Mobile computing devices like laptops, notebook PCs etc are becoming common nowadays. The heart of every PC whether a desktop or mobile PC is the microprocessor. Several microprocessors are available in the market for desktop PCs from companies like Intel, AMD, Cyrix etc.
The mobile computing market has never had a microprocessor specifically designed for it. The microprocessors used in mobile PCs are optimized versions of the desktop PC microprocessor.
Mobile computing makes very different demands on processors than desktop computing. Those desktop PC processors consume lots of power, and they get very hot. run through the airport. . The market will still reject a newly designed microprocessor with low power consumption if the performance is poor. So any attempt in this regard must have a proper 'performance-power' balance to ensure commercial success
Crusoe is the new microprocessor, which has been designed specially for the mobile computing market .It has been, designed after considering the above-mentioned constraints. A small Silicon Valley startup company called Transmeta Corp developed this microprocessor.
The concept of Crusoe is well understood from the simple sketch of the processor architecture, called 'amoebaâ„¢. i.e. it has a software part and a hardware part with the software layer surrounding the hardware unit.
The role of software is to act as an emulator to translate x86 binaries into native code at run time. Crusoe is a 128-bit microprocessor fabricated using the CMOS process. The chip's design is based on a technique called VLIW to ensure design simplicity and high performance.
The other two technologies using are Code Morphing Software and LongRun Power Management. The crusoe hardware can be changed radically without affecting legacy x86 software.
CRUSOE PROCESSOR VLIW HARDWARE
VLIW stands for Very Long Instruction Word. VLIW is a method that combines multiple standard instructions into one long instruction word. This word contains instns that can be executed at the same time on separate chips or different parts of the same chip. It provides explicit parallelism, i.e. executing more than one basic (primitive) instn at a time.
Trace scheduling is an important technique in VLIW processing. i.e. the compiler processes the code and determines which path is the most frequently traveled, and then optimizes this path. Basic blocks that compose the path are separated from the other basic blocks. The path is then optimized and rejoined with the other basic blocks using split and rejoin blocks.
Basic principles of VLIW Architecture
Dynamic scheduling is another important method when compiling VLIW code. The process called split-issue splits the code into two phases,
¢ This allows for multiple instns, instns having certain delays etc to execute at the same time. H/W support is needed to implement and needs delay buffers and temporary variable space (TVS) in the h/w.
¢ The TVS is needed to store results when they come in. The results computed in phase two are stored in temporary variables and are loaded into the appropriate phase one register when they are needed.
VLIW has been described as a natural successor to RISC, whose instn set consists of simple instructions (RISC-like). because it moves complexity from the hardware to the compiler, allowing simpler, faster processors. One objective of VLIW is to eliminate the complicated instruction scheduling. The compiler must assemble many primitive operations into a single "instruction word" such that the multiple functional units are kept busy.
Crusoe VLIW in Microprocessor
With the Code Morphing software handling x86 compatibility, Transmeta hardware designers created a very simple, high-performance, VLIW engine with two integer units,
¢ floating-point unit
¢ memory (load/store) unit
¢ branch unit.
¢ A Crusoe processor long instruction word, called a molecule, can be 64 bits or 128 bits long and contain up to four RISC-like nstructions,called atoms. All atoms within a molecule are executed in parallel, and the molecule format directly determines how atoms get routed to functional units; this greatly simplifies the decode and dispatch hardware
CRUSOE PROCESSOR ARCHITECTURE
The Crusoe microprocessor is available in the market in the following versions:
¢ TM3120
¢ TM3200
¢ TM5400
¢ TM5600.
¢ The basic architecture of all the above models are same except for some minor changes since various models have been introduced for different segments of the mobile computing market.
¢ The Crusoe Processor incorporates integer and floating point execution units, separate instruction and data caches, a level-2 write-back cache, memory management unit, and multimedia instructions. In addition to these traditional processor features, there are some additional units, which are usually part of the core system logic that surrounds the microprocessor.
¢ The VLIW processor, in combination with Code Morphing software and the additional system core logic units, allow the Crusoe Processor to provide a highly integrated, ultra-low power, high performance platform solution for the x 86 mobile markets.
Processor Core
The Crusoe Processor core architecture is relatively simple by conventional standards. It is based on a VLIW 128-bit instn set. Within this VLIW architecture, the control logic of the processor is kept very simple and s/w is used to control the scheduling of instns.
This allows a simplified and very straightforward h/w implementation with an in-order 7-stage integer pipeline and a 10-stage floating-point.
This cache architecture assures maximum internal memory bandwidth for performance intensive mobile applications, while maintaining the same low-power implementation that provides a superior performance-to-power consumption ratio relative to previous x86 implementations.
Execution h/w for logical, arithmetic, shift, and floating point instns, as in conventional processors, the Crusoe has very distinctive features from traditional x86 designs
Integrated DDR SDRAM Memory Controller
¢ DDR SDRAM interface is the highest performance memory interface available on the Crusoe. The DDR SDRAM controller supports only Double Data Rate (DDR) SDRAM and transfers data at a rate that is twice the clock frequency of the inter-face.
Integrated SDR SDRAM Memory Controller
¢ The SDR SDRAM memory controller supports up to four banks, equivalent to two Small Outline Dual In-line Memory Modules (SO-DIMMS), of Single Data Rate (SDR) SDRAM that can be configured as 64-bit or 72-bit
¢ .These SO-DIMMs can be populated with 64M-bit, 128M-bit or 256M-bit devices.
¢ All SO-DIMMs must use the same frequency SDRAMs, but there are no restrictions on mixing different SO- DIMM configurations into each SO-DIMM slot.
¢ The frequency setting for the SDR SDRAM interface is initialized during the power-on boot sequence.
Integrated PCI Controller
¢ The Crusoe Processor includes a PCI bus controller that is PCI 2.1 compliant.
¢ The PCI bus is 32 bits wide, operates at 33 MHz, and is compatible with 3.3V signal levels.
¢ It is not 5V tolerant, however. The PCI controller on provides a PCI host bridge, the PCI bus arbiter, and a DMA controller.
Serial ROM Interface
¢ The Crusoe serial ROM interface is a five-pin interface used to read data from a serial flash ROM.
¢ The flash ROM is 1M-byte in size and provides non-volatile storage for the CMS.
¢ During the boot process, the Code Morphing code is copied from the ROM to the Code Morphing memory space in SDRAM. Once trans-erred, the Code Morphing code requires 8 to 16M-bytes of memory space.
¢ The portion of SDRAM space reserved for CMS is not visible to x86 code.
¢ This interface may also be used for in-system reprogramming of the flash ROM
FEATURES OF VARIOUS CRUSOE PROCESSORS
¢ VLIW processor and x86 Code Morphing software provide x86 compatible mobile platform solution.
¢ Processor core operates at 366 and 400 MHz.
¢ PCI (Peripheral Component Interface) bus controller
with 33 MHz, 3.3V interface
¢ Advanced power management features and very-low power operation
extend mobile battery life
¢ Full System Management Mode (SMM) support
¢ Compact 474-pin ceramic BGA (Ball Grid Array) package
¢ LongRun advanced power management with ultra-low power operation
Application:
¢ Prototype web based application
¢ Crusoe Special Embedded (SE) processors
¢ A processor that executes every instruction one after the other may use processor resources inefficiently, potentially leading to poor performance.
¢ The performance can be improved by executing different sub-steps of sequential instructions simultaneously or even executing multiple instructions entirely
¢ Crusoe processor support Symbian Os software.
Contents :
1. Introduction
2. CRUSOE PROCESSOR
VLIW HARDWARE
3. Crusoe VLIW in Microprocessor
4. Processor Core
5. SDRAM Memory Controller
6. Features
7. Application