22-06-2013, 04:04 PM
Design of a Reversible Floating-Point Adder Architecturea
Design of a Reversible.pdf (Size: 1.22 MB / Downloads: 37)
Abstract
The study of reversible circuits holds great
promise for emerging technologies. Reversible circuits offer the
possibility for great reductions in power consumption, and
quantum computers will require logically reversible digital
circuits. Many different reversible implementations of logical
and arithmetic units have been proposed in the literature, but
very few reversible floating-point designs exist. Floating-point
operations are needed very frequently in nearly all computing
disciplines, and studies have shown floating-point addition to
be the most oft used floating-point operation. In this paper we
present for the first time a reversible floating-point adder that
closely follows the IEEE754 specification for binary floatingpoint
arithmetic. Our design requires reversible designs of a
controlled swap unit, a subtracter, an alignment unit, signed
integer representation conversion units, an integer adder, a
normalization unit, and a rounding unit. We analyze these
major components in terms of quantum cost, garbage outputs,
and constant inputs.
INTRODUCTION
eversible computing differs from conventional
computing in that it performs the computation in a
logically reversible way: The output of a (fully) reversible
circuit always uniquely identifies the input. Circuits can take
advantage of this logical reversibility to reduce power by
reusing the information instead of discarding it: Landauer
showed that any time a bit of information is discarded, it
equates to some quantum of energy lost as heat [1].
Moreover, Bennett has given a theoretical model of a
reversible computer [2].
Modern computers use conventions for representing noninteger
numbers, the most widespread of which is the
IEEE754 Standard for Floating-Point Arithmetic [3]. This
standard defines binary representation for floating-point
numbers of varying precision, giving specific examples of the
binary32 (or single precision) format, binary64 (or double
precision) format, and it defines operations on floating-point
numbers. Floating-point addition is the most frequently used
floating-point operation [4], and yet to our knowledge no
attempt has been made at a reversible floating-point adder
architecture; only a reversible binary32 floating-point
multiplier architecture has been proposed [5].
REVERSIBLE LOGIC PRIMITIVES
Many traditional logic gates such as the AND, OR,
NAND, NOR, and XOR gates are fundamentally irreversible.
That is to say that the output combination of any of these
gates does not expose the input combination that caused the
output. Thus we have a need for primitive reversible logic
gates. Researchers already have developed many such gates,
including the Feynman, Toffoli, Peres, Fredkin, HNG, and
TSG gates [6, 7, 8, 10]. Each gate is defined by the number
of inputs and outputs it has (reversible gates must have equal
numbers of inputs and outputs) and its Boolean output
functions. See Fig. 1 for details on the Feynman and Fredkin
gates.
FLOATING-POINT ADDITION
The Algorithm
Given two floating-point numbers (each having sign,
biased exponent, and trailing significand fields) to be added,
the IEEE754 Standard for Floating-Point Arithmetic details
how their sum can be found [3]: First, if the exponents are
not equal, the smaller is incremented until it aligns with the
larger. To align the floating-point number with the smaller
exponent without altering its value, its respective trailing
significand must be shifted one place to the right for every
time the exponent is incremented. Once the exponents are
equal, the significands can be summed. The sum is then
normalized and rounded. Fig. 2 illustrates the block-level
schematic of the architecture our proposed reversible
floating-point adder design uses.
Reversible Normalization
After the sum of the trailing significands has been
converted back into sign-magnitude representation, the sign
bit is connected directly to the final stage as the sign of the
floating-point sum, and the magnitude may need to be
normalized. This normalization step may involve either left
shifting or right shifting. If a right shift is required, only a
right shift of a single position will be required. Otherwise a
left shift of possibly several placed may be required. A
synchronous floating-point adder architecture might
accomplish this behavior using synchronous leading-one
detectors and synchronous shift registers, but in keeping with
our asynchronous reversible design methodology, we design
a completely asynchronous reversible normalization unit.
RESULTS AND CONCLUSION
Researchers have worked hard at designing, automating,
and synthesizing reversible logic and quantum arithmetic
gates [15, 16, 17, 18, 19], but very little has been focused on
investigating the design of reversible floating-point units. In
this work we present a novel reversible binary32 (single
precision) floating-point adder architecture. This architecture
we analyze in terms of quantum cost, garbage outputs, and
constant inputs. Table VI shows that all three reversible
metrics are dominated by the reversible alignment and
reversible normalization components. Future related work
could optimize one or more of these components.