25-04-2014, 04:57 PM
ISim In-Depth Tutorial
ISim Overview
The ISim In-Depth Tutorial provides Xilinx® designers with a detailed introduction of the
ISim simulation tool.
This tutorial is designed for running the ISim tool on a Windows environment. To run
certain steps successfully in other operation systems, some modifications might be
required.
ISim is a Hardware Description Language (HDL) simulator that lets you perform
functional (behavioral) and timing simulations for VHDL, Verilog, and mixed-language
designs. The ISim environment comprises the following key elements:
• vhpcomp (VHDL) and vlogcomp (Verilog) parsers
• fuse (HDL elaborator and linker) command
• Simulation executable
• ISim Graphical User Interface (GUI)
Tutorial Flow
This tutorial provides a flow in which you can use ISim for performing a functional
(behavioral) simulation from the Project Navigator in the ISE® Design Suite.
In this flow, you launch ISim using one of the simulation processes available in the Project
Navigator. You use the Project Navigator to create a project and implement the design in a
Xilinx FPGA.
The tutorial files contain sources that are not in Hardware Description Language (HDL),
and, thus demonstrate how Project Navigator converts these sources to HDL source files
that ISim can then compile.
Also, there is a chapter that shows you how to do the same work in a Standalone ISim
mode, where you simulate your design by creating your own ISim project files and
running the HDL linker and simulation executable in command line or batch file mode.
Compile the Design
The ISim integrated flow lets you perform behavioral and timing simulations of your
design in either the ISE Project Navigator tool.
In this tutorial flow, you create an ISE project for the tutorial design first. You then set
behavioral simulation properties, and launch the ISim simulator to perform a behavioral
simulation of the design.