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OVERVIEW
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OVERVIEW
The ADSP-2100 family is a collection of programmable single-chip
microprocessors that share a common base architecture optimized for
digital signal processing (DSP) and other high-speed numeric processing
applications. The various family processors differ principally in the type
of on-chip peripherals they add to the base architecture. On-chip memory,
a timer, serial port(s), and parallel ports are available in different members
of the family. In addition, the ADSP-21msp58/59 processors include an
on-chip analog interface for voiceband signal conversion.
This manual provides the information necessary to understand and
evaluate the processors’ architecture, and to determine which device best
meets your needs for a particular application. Together with the data
sheets describing the individual devices, this manual provides all the
information required to design a DSP system. Complete reference material
for programmers is also included.
Memory And System Interface
In each ADSP-21xx processor, four on-chip buses connect internal memory with
the other functional units: Data Memory Address bus, Data Memory Data bus,
Program Memory Address bus, and Program Memory Data bus. A single
external address bus and and a single external data bus are extended off-chip;
these buses can be used for either program or data memory access.
External devices can gain control of the processor’s buses with the bus request
and grant signals (BR, BG). The ADSP-21xx processors can continue running
while the buses are granted to another device, as long as an external memory
operation is not required.
1 Introduction
1 – 4
The ADSP-21xx processors support memory-mapped peripherals with
programmable wait state generation.
Boot circuitry provides for loading on-chip program memory
automatically after reset. This can be done either through the memory
interface from a single low-cost EPROM, through the host interface port
from a host processor, or through the BDMA port of the ADSP-2181.
Multiple programs can be selected and loaded with no additional
hardware.
ADSP-2100 family processors differ in their response to interrupts. In all
cases, however, the program sequencer allows the processor to respond
with minimum latency. Interrupts can be nested with no additional
latency. External interrupts can be configured as edge- or level-sensitive.
Internal interrupts can be generated from the timer, the host interface port,
the serial ports, and the BDMA port.
Computational Units
Every processor in the ADSP-2100 family contains three independent, fullfunction
computational units: an arithmetic/logic unit (ALU), a
multiplier/accumulator (MAC) and a barrel shifter. The computation
units process 16-bit data directly and provide hardware support for
multiprecision computation as well.
The ALU performs a standard set of arithmetic and logic operations in
addition to division primitives. The MAC performs single-cycle multiply,
multiply/add and multiply/subtract operations. The shifter performs
logical and arithmetic shifts, normalization, denormalization, and deriveexponent
operations. The shifter implements numeric format control
including multiword floating-point representations. The computational
units are arranged side-by-side instead of serially so that the output of any
unit may be the input of any unit on the next cycle. The internal result ®
bus directly connects the computational units to make this possible.
Introduction 1
1 – 7
All three units contain input and output registers which are accessible
from the internal data memory data (DMD) bus. Computational
operations generally take their operands from input registers and load the
result into an output register. The registers act as a stopover point for data
between memory and the computational circuitry. This feature introduces
one level of pipelining on input, and one level on output. The R bus allows
the result of a previous computation to be used directly as the input to
another computation. This avoids excessive pipeline delays when a series
of different operations are performed.
Timer
The programmable interval timer provides periodic interrupt generation.
An 8-bit prescaler register allows the timer to decrement a 16-bit count
register over a range from each cycle to every 256 cycles. An interrupt is
generated when this count register reaches zero. The count register is
automatically reloaded from a 16-bit period register and the count
resumes immediately.
1.3.3 Host Interface Port (ADSP-2111, ADSP-2171, ADSP-21msp5x)
The host interface port (HIP) is a parallel I/O port that allows for an easy
connection to a host processor. Through the HIP, an ADSP-21xx DSP can
be used as a memory-mapped peripheral of the host. The HIP operates in
parallel with and asynchronous to the ADSP-21xx’s computational core
and internal memory. The host interface port consists of registers through
which the ADSP-21xx and the host processor pass data and status
information. The HIP can be configured for: an 8-bit data bus or 16-bit
data bus; a multiplexed address/data bus or separate address and data
buses; and separate read and write strobes or a read/write strobe and a
data strobe.
1.3.4 DMA Ports (ADSP-2181)
The ADSP-2181 contains two DMA ports, and Internal DMA Port and a
Byte DMA Port. The IDMA port provides an efficient means of
communication between a host system and the DSP. The port is used to
access the on-chip program memory and data memory of the DSP with
only one cycle per word of overhead. The IDMA port has a 16-bit
multiplexed address and data bus and supports 24-bit program memory.
The IDMA port is completely asynchronous and can be written to while
the ADSP-2181 is operating at full speed.
The internal memory address is latched and then automatically
incremented after each IDMA transaction. An external device can
therefore access a block of sequentially addressed memory by specifying
only the starting address of the block.
The byte memory DMA controller allows loading and storing of program
instructions and data using the byte memory space. The BDMA circuit is
able to access the byte memory space while the processor is operating
normally and steals only one processor cycle per 8-, 16- or 24-bit word
transferred.
ORGANIZATION OF THIS MANUAL
This manual is organized as follows.
Chapters 2, 3, and 4 describe the core architectural features shared by all
members of the ADSP-2100 family:
• Chapter 2, “Computational Units,” describes the functions and internal
organization of the arithmetic/logic unit (ALU), the multiplier/
accumulator (MAC), and the barrel shifter.
• Chapter 3, “Program Control,” describes the program sequencer,
interrupt controller and status and condition logic.
• Chapter 4, “Data Transfer,” describes the data address generators
(DAGs) and the PMD-DMD bus exchange unit.
Chapters 5, 6, 7, and 8 describe the additional functional units included in
different members of the ADSP-2100 family. (See Table 1.1 for a list of the
functions included in each device.)
• Chapter 5, “Serial Ports,” describes the serial ports, SPORT0 and
SPORT1.
• Chapter 6, “Timer,” explains the programmable interval timer.
• Chapter 7, “Host Interface Port,” describes the operation of the host
interface port, including boot loading and software reset.
• Chapter 8, “Analog Interface,” describes the operation and the internal
architecture of the ADSP-21msp58/59’s analog interface.
Chapters 9 and 10 describe the behavior of the ADSP-21xx processors
from the point of view of external memory and control logic:
• Chapter 9, “System Interface,” discusses the issue of system clocking,
and describes the processors’ control interface, the software reboot
function, and the powerdown mode.
1 Introduction
1 – 12
• Chapter 10, “Memory Interface,” describes the data and program
memory spaces. This chapter describes both internal and external
memory, including the use of boot memory space. A special section is
devoted to the ADSP-2181, since its memory interface differs from that
of the other family processors.
Chapter 11, “DMA Ports,” describes the operation of the ADSP-2181’s
IDMA and BDMA features.
Chapter 12, “Programming Model,” gives a functional description of the
processor resources—such as registers—as they appear in software.
Chapter 13, “Hardware Examples,” gives examples of system designs
using the ADSP-21xx processors. Each example illustrates the solution to a
different system design issue, using block diagrams, explanatory text, and
programs or timing diagrams as needed.
Chapter 14, “Software Examples,” provides illustrative code for some
important DSP and numerical algorithms.
Chapter 15, “Instruction Set Reference,” provides a detailed description of
each ADSP-21xx instruction.
The Appendices provide reference material and further details on specific
issues:
• Appendix A, “Instruction Coding,” gives the complete set of opcodes
and specifies the bit patterns for choices within each field of the
instruction word.
• Appendix B, “Division Exceptions,” describes signed and unsigned
division.
• Appendix C, “Numeric Formats,” describes the fixed-point numerical
formats directly supported by the ADSP-2100 family, discusses block
floating-point arithmetic, and tells how to handle the results of
multiplication for operands of various formats.
• Appendix D, “Interrupt Vector Addresses,” lists the interrupt vectors
of each family processor.
• Appendix E, “Control/Status Registers,” summarizes the processors’
control and status registers.