02-10-2017, 11:37 AM
The parity generation technique is one of the most commonly used error detection techniques for data transmission. In digital systems, when binary data is transmitted and processed, the data may be subject to noise such that the noise can alter 0s (of data bits) to 1s and 1s to 0s. Therefore, parity bit is added to the word containing data to make the number 1 is even or odd. This is used to detect errors during the transmission of binary data. The message containing the data bits together with the parity bit is transmitted from the transmitting node to the receiving node.
At the receiving end, the number of 1s is counted in the message and if it does not match the transmitted one, then it means that there is an error in the data. A parity generator is a combinational logic circuit that generates the parity bit in the transmitter. On the other hand, a circuit that checks for parity in the receiver is called a parity checker. A combined parity generator circuit and devices and parity controllers are commonly used in digital systems to detect single-bit errors in the transmitted data word.
The sum of the data bits and the parity bits may be even or odd. In even parity, the added parity bit will cause the total number of 1s to be an even number, while in odd parity the added parity bit will cause the total number of odd 1s.
The basic principle involved in the implementation of parity circuits is that the sum of the odd number of 1s is always 1 and the sum of the even number of 1s is always zero. Such error detection and correction can be implemented using Ex-OR gates (since the Ex-OR output produces zero output when there are even numbers of inputs).
At the receiving end, the number of 1s is counted in the message and if it does not match the transmitted one, then it means that there is an error in the data. A parity generator is a combinational logic circuit that generates the parity bit in the transmitter. On the other hand, a circuit that checks for parity in the receiver is called a parity checker. A combined parity generator circuit and devices and parity controllers are commonly used in digital systems to detect single-bit errors in the transmitted data word.
The sum of the data bits and the parity bits may be even or odd. In even parity, the added parity bit will cause the total number of 1s to be an even number, while in odd parity the added parity bit will cause the total number of odd 1s.
The basic principle involved in the implementation of parity circuits is that the sum of the odd number of 1s is always 1 and the sum of the even number of 1s is always zero. Such error detection and correction can be implemented using Ex-OR gates (since the Ex-OR output produces zero output when there are even numbers of inputs).