02-10-2017, 12:04 PM
A linear feedback shift register (LFSR) is assembled by N number of flip flops connected in series and a combinational logic usually xor gate. An LFSR can generate a random numerical sequence that acts as a cipher in cryptography. A known text encoded along a long PN sequence, in order to improve the security sequence made longer is to say 128 bits; requiring a long chain of flip-flops leads to greater energy consumption. In this work, a new random sequence generator circuit using double-triggered flip-flop has been proposed. Data has been generated at each edge of the flip-flop instead of a single edge. A DETFF-LFSR can generate random number requires with less number of clock cycle, minimizes the number of flip-flop result in energy saving. In this paper we focus on the design of the competent power test pattern generator (TPG) using four double edge flip-flops triggered as the basic building block, in general there is a power reduction of about 25% through the use of these techniques.