03-10-2017, 11:14 AM
The network on chip or the network in a chip (NoC or NOC) is a communication subsystem in an integrated circuit (commonly called "chip"), typically between intellectual property (IP) cores in a system in a chip (SoC) . NoCs can span synchronous and asynchronous clock domains or use non-synchronized asynchronous logic. NoC technology applies network theory and methods to on-chip communication and brings significant improvements over conventional bar and bus interconnects. NoC improves the scalability of SoCs and the energy efficiency of complex SoCs compared to other designs.
A number of research studies have demonstrated the viability and advantages of Network-on-Chip (NoC) over traditional bus-based architectures. This white paper summarizes the limitations of traditional bus-based approaches, introduces the benefits of the generic NoC concept, and provides specific data on Arteris NoC, the first commercial implementation of such architectures. Using a generic design example, we offer detailed comparisons of the scalability, performance and area of traditional buses or crossbars compared to the Arteris NoC.
The cables in the NoC links are shared by many signals. A high level of parallelism is achieved because all the links in the NoC can operate simultaneously in different data packets. Therefore, as the complexity of integrated systems continues to grow, a NoC provides improved performance (such as throughput) and scalability compared to previous communication architectures (for example, dedicated point-to-point signal cables, shared buses or segmented buses with bridges). Of course, the algorithms must be designed in such a way that they offer a great parallelism and, therefore, they can use the potential of NoC.
A number of research studies have demonstrated the viability and advantages of Network-on-Chip (NoC) over traditional bus-based architectures. This white paper summarizes the limitations of traditional bus-based approaches, introduces the benefits of the generic NoC concept, and provides specific data on Arteris NoC, the first commercial implementation of such architectures. Using a generic design example, we offer detailed comparisons of the scalability, performance and area of traditional buses or crossbars compared to the Arteris NoC.
The cables in the NoC links are shared by many signals. A high level of parallelism is achieved because all the links in the NoC can operate simultaneously in different data packets. Therefore, as the complexity of integrated systems continues to grow, a NoC provides improved performance (such as throughput) and scalability compared to previous communication architectures (for example, dedicated point-to-point signal cables, shared buses or segmented buses with bridges). Of course, the algorithms must be designed in such a way that they offer a great parallelism and, therefore, they can use the potential of NoC.