25-01-2011, 04:03 PM
Dynamic cache management technique to reduce the energy in a high performance processor.
The processors exploit the instruction level parallelism to supply instruction and data to the data path so that the execution rate is kepty as high as possible. High energy requireemnts for the on-chip-I-cache entails high energy demand. To reduce the amount of energy dissipated per instruction access, an additional L0 cache is designed. It acts as the primary cache of the processor storing the most frequentlyu accessed instructions. This cache makes use of the properties like the temoporalities of code and the decisions can be taken on the fly while the instruction is executing.
Dynamic management scheme.
The most frequently accessed instructiona are kept in the L0 cache. Energy reduction is aimed without the odification of the existing hardware. A reliable solution to this problem is provided by the branch prediction schene together with the confidence estimator mechanism. The branch behaviour of the future is estimated on the basis of the branches previously taken . The steady state behaviour of the branch is further predicted by the confidence estimator.
For further details, see:
http://www.cs.york.ac.uk/rts/docs/SIGDA-...s/04_1.pdf
http://www.scribddoc/7148877/Dynamic-Cache-Management
The processors exploit the instruction level parallelism to supply instruction and data to the data path so that the execution rate is kepty as high as possible. High energy requireemnts for the on-chip-I-cache entails high energy demand. To reduce the amount of energy dissipated per instruction access, an additional L0 cache is designed. It acts as the primary cache of the processor storing the most frequentlyu accessed instructions. This cache makes use of the properties like the temoporalities of code and the decisions can be taken on the fly while the instruction is executing.
Dynamic management scheme.
The most frequently accessed instructiona are kept in the L0 cache. Energy reduction is aimed without the odification of the existing hardware. A reliable solution to this problem is provided by the branch prediction schene together with the confidence estimator mechanism. The branch behaviour of the future is estimated on the basis of the branches previously taken . The steady state behaviour of the branch is further predicted by the confidence estimator.
For further details, see:
http://www.cs.york.ac.uk/rts/docs/SIGDA-...s/04_1.pdf
http://www.scribddoc/7148877/Dynamic-Cache-Management