31-03-2012, 11:05 AM
FinFET Technology
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INTRODUCTION
The introduction of FinFET Technology has opened new chapters in Nano-technology. Simulations show that FinFET structure should be scalable down to 10 nm. Formation of ultra thin fin enables suppressed short channel effects. It is an attractive successor to the single gate MOSFET by virtue of its superior electrostatic properties and comparative ease of manufacturability. Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high speed devices and in very large scale integrated circuits.
The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure.The limits most often cited are control of the density and location of dopants providing high I on /I off ratio and finite subthreshold slope and quantum-mechanical tunneling of carriers through thin gate from drain to source and from drain to body. The channel depletion width must scale with the channel length to contain the off-state leakage I off. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult. The gate oxide thickness tox must also scale with the channel length to maintain gate control, proper threshold voltage VT and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin.
ARCHITECTURE
This method provides a SiGe-based bulk integration scheme for generating FinFET devices on a bulk Si substrate in which a simple etch, mask, ion implant set of sequences have been added to accomplish good junction isolation while maintaining the low capacitance benefits of FinFETs. Specifically, the method of the present invention includes the steps of: providing a structure including a bottom Si layer and a patterned stack comprising a SiGe layer and a top Si layer on said bottom Si layer; forming a well region and isolation regions via implantation within said bottom Si layer; forming an undercut region beneath said top Si layer by etching back said SiGe layer; and filling said undercut with a dielectric to provide device isolation, wherein said dielectric has an outer vertical edge that is aligned to an outer vertical edge of said top Si layer.
ADVANTAGES
Due to their high immunity to short channel effects, importance of MOSFET with multiple gates (MUGFET) or FinFETs are increased by technologists for sub-100nm. Especially for the digital applications, numerous FinFET realizations have reported with effective and improved feasibility, economy and performance with respect to up to date CMOS bulk technologies.
Since, the FinFETs have better electrostatic channel control characteristic with improved turn off, they are considered as promising candidate for the future‟s fulfilling CMOS device demands.
APPLICATIONS
FinFETs have a wide variety of applications. Some of these are pointed here.
Transconductance Amplifier Using Finfet Technology
Due to their high immunity to short channel effects, importance of MOSFET with multiple gates (MUGFET) or FinFETs are increased by technologists for sub-100nm . Especially for the digital applications, numerous FinFET realizations have reported with effective and improved feasibility, economy and performance with respect to up to date CMOS bulk technologies . Since, the FinFETs have better electrostatic channel control characteristic with improved turn off, they are considered as promising candidate for the future‟s fulfilling CMOS device demands. In addition to excellent channel control, the FinFET transistors also offer approximately twice the on-current because of the two channels, even without channel doping. This is beneficial for the carrier mobility and results in a low gate leakage at the same time
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INTRODUCTION
The introduction of FinFET Technology has opened new chapters in Nano-technology. Simulations show that FinFET structure should be scalable down to 10 nm. Formation of ultra thin fin enables suppressed short channel effects. It is an attractive successor to the single gate MOSFET by virtue of its superior electrostatic properties and comparative ease of manufacturability. Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high speed devices and in very large scale integrated circuits.
The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure.The limits most often cited are control of the density and location of dopants providing high I on /I off ratio and finite subthreshold slope and quantum-mechanical tunneling of carriers through thin gate from drain to source and from drain to body. The channel depletion width must scale with the channel length to contain the off-state leakage I off. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult. The gate oxide thickness tox must also scale with the channel length to maintain gate control, proper threshold voltage VT and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin.
ARCHITECTURE
This method provides a SiGe-based bulk integration scheme for generating FinFET devices on a bulk Si substrate in which a simple etch, mask, ion implant set of sequences have been added to accomplish good junction isolation while maintaining the low capacitance benefits of FinFETs. Specifically, the method of the present invention includes the steps of: providing a structure including a bottom Si layer and a patterned stack comprising a SiGe layer and a top Si layer on said bottom Si layer; forming a well region and isolation regions via implantation within said bottom Si layer; forming an undercut region beneath said top Si layer by etching back said SiGe layer; and filling said undercut with a dielectric to provide device isolation, wherein said dielectric has an outer vertical edge that is aligned to an outer vertical edge of said top Si layer.
ADVANTAGES
Due to their high immunity to short channel effects, importance of MOSFET with multiple gates (MUGFET) or FinFETs are increased by technologists for sub-100nm. Especially for the digital applications, numerous FinFET realizations have reported with effective and improved feasibility, economy and performance with respect to up to date CMOS bulk technologies.
Since, the FinFETs have better electrostatic channel control characteristic with improved turn off, they are considered as promising candidate for the future‟s fulfilling CMOS device demands.
APPLICATIONS
FinFETs have a wide variety of applications. Some of these are pointed here.
Transconductance Amplifier Using Finfet Technology
Due to their high immunity to short channel effects, importance of MOSFET with multiple gates (MUGFET) or FinFETs are increased by technologists for sub-100nm . Especially for the digital applications, numerous FinFET realizations have reported with effective and improved feasibility, economy and performance with respect to up to date CMOS bulk technologies . Since, the FinFETs have better electrostatic channel control characteristic with improved turn off, they are considered as promising candidate for the future‟s fulfilling CMOS device demands. In addition to excellent channel control, the FinFET transistors also offer approximately twice the on-current because of the two channels, even without channel doping. This is beneficial for the carrier mobility and results in a low gate leakage at the same time