12-04-2012, 05:01 PM
IMPROVED 2kW SOLAR INVERTER WITH WIDE INPUT VOLTAGE RANGE
5kw inverter sim.pdf (Size: 330.98 KB / Downloads: 193)
INTRODUCTION
Switching mode PWM converters have high efficiency and
are used when high output power has to be maintained
(e.g. solar and renewable energy applications, etc.), but
. also in the industrial field of applications. The starting
point of ow investigations was a project for a solar inverter
with the goal of very high efficiency over an input voltage
variation of 1 :2 (1 20-24OV). Driving stages for high
dynamic actuators and motor drives up to several kilowatts
are another field of application. In this paper a new concept
is shown which increases the input and output signal
quality to meet high mains quality and reduce EMC
problematic.
MULTI PHASEP WM INVERTER
To overcome the main drawback of convential solutions,
the very high current in the output power stages of DC-to-
AC inverters at low input voltage ratings current sharing
by parallel connection of the power switches (in general
MOSFETs) is used (e.g. SI to S4 in Fig.2 consist of several
discrete power MOSFETs). This solution cannot remove
the high current amplitudes in the output inductors and
filtering capacitors
PRINCIPLE MODE OF OPERATION
The topology, analyzed in this paper (left section of
Fig. 3.), uses a single, dual and three phase delay PWM
mode depending to the required output voltage and the
aviable inpout voltage. The number of power stages in use
and the phase delay is controlled dynamically. This leads to
a further improvement in the over all efficiency of the
inverter even if here are more power switches used
compared to the conventional converter type
PRINCIPARLEA LISATION
A principal concept of switching ripple minimization
depicted in Fig. 3 was analyzed in detail and a laboratory
prototype was breadboarded. The sample inverter was
designed for a solar application operating at 120 to 240V
DC-input and 230V at AC-output. Here, only the DC-to-
DC converter is a point of interest. The DC-to-AC inverter
is a PWM-type topology and will be analyzed in a further
paper.
The output power stages are build up with cheap mass
product semiconductors and low cost fix-inductors.
Paralleling of this small and rather simple stages lead to a
high power inverter with excellent efficiency compared to
conventional PWM inverters.
CONCLUSION
This new solution will improve the disadvantage of parallel
operation of output switches in the power stages in
conventional converters. Due to the reduced current in each
of the stages the efficiency will increase significantly. The
ripple of the input current is shared between the different
stages which can help to reduce the input capacitor. Also
the resulting switching frequency rises with the number of
active stages. This results to a more silent (EMV) design.
It's power stage consists of three PWM halve-bridges
operating in parallel. Each stage switching at SOkHz with a
phase delay of 120' to the previous. The maximum peak
current of each output stage is less than 10A.