18-06-2012, 05:59 PM
NANOELECTRONICS
nanoelectronicsfinal-100114091007-phpapp02.ppt (Size: 971.5 KB / Downloads: 58)
MOORE’S LAW
According to Moore’s Law, the number of transistors that will fit on a silicon chip doubles every eighteen months.
Presently, microprocessors have more than forty million transistors
By the year 2020, the trend line of Moore’s law states that there should be a one nanometer feature size.
SCALING PRINCIPLES
For designing nano FET apart from channel length, other parameters like doping, voltages etc. are to be also scaled.
SCALING LIMITS OF MOSFET
Technical problem: For channel length<30nm , insulating SiO2 is expected to be less than 2nm thick. This thin layer causes gate dielectric tunneling
Physical problem: For channel length<10nm, direct source-drain tunneling occurs.
RESONANT TUNNELING IN NANO DEVICES
RT is observed in hetero-structure semiconductor devices made from pairs of different alloys III-V alloys.
Eg. AlGaAs/GaAs/AlGaAs diodes
nanoelectronicsfinal-100114091007-phpapp02.ppt (Size: 971.5 KB / Downloads: 58)
MOORE’S LAW
According to Moore’s Law, the number of transistors that will fit on a silicon chip doubles every eighteen months.
Presently, microprocessors have more than forty million transistors
By the year 2020, the trend line of Moore’s law states that there should be a one nanometer feature size.
SCALING PRINCIPLES
For designing nano FET apart from channel length, other parameters like doping, voltages etc. are to be also scaled.
SCALING LIMITS OF MOSFET
Technical problem: For channel length<30nm , insulating SiO2 is expected to be less than 2nm thick. This thin layer causes gate dielectric tunneling
Physical problem: For channel length<10nm, direct source-drain tunneling occurs.
RESONANT TUNNELING IN NANO DEVICES
RT is observed in hetero-structure semiconductor devices made from pairs of different alloys III-V alloys.
Eg. AlGaAs/GaAs/AlGaAs diodes