03-07-2012, 04:48 PM
Design Universal Asynchronous Receiver/Transmitter
Design Universal Asynchronous ReceiverTransmitter.docx (Size: 916.87 KB / Downloads: 63)
INTRODUCTION
This thesis portrays a novel architecture of Universal Asynchronous Receiver Transmitter. UARTs are used for asynchronous serial data communication between remote embedded systems. The UART is for interfacing computers or microprocessors to an asynchronous serial data channel. The receiver converts serial start, data, parity and stop bits. The transmitter converts parallel data into serial form and automatically adds start, parity and stop bits. The data word length can be 5, 6, 7 or 8 bits. Parity may be odd or even. Parity checking and generation can be inhibited. The stop bits may be one or two or one and one-half when transmitting 5-bit code.
Synchronous Serial Transmission
Synchronous serial transmission requires that the sender and receiver share a clock with one another, or that the sender provide a strobe or other timing signal so that the receiver knows when to “read” the next bit of the data. In most forms of serial Synchronous communication, if there is no data available at a given instant to transmit, a fill character must be sent instead so that data is always being transmitted. Synchronous communication is usually more efficient because only data bits are transmitted between sender and receiver, and synchronous communication can be more costly if extra wiring and circuits are required to share a clock signal between the sender and receiver.
Receiver Module
The serial receiver section also contains an 8-bit Receiver Buffer Register (RBR) and Receiver Shift Register (RSR). The status of RBR can be provided by either independent pin RxRDYn or the Receiver Data available flag (DR) in LSR.
Since the serial frame is asynchronous to the receiving clock, a high to low transition of SIN pin will be treated as the Start bit of a frame. However, in order to avoid receiving a incorrect data due to SIN signal noise, the False Start Bit Detection feature is implemented in the design which requires the Start bit to be low at least 50% of the receiv- ing baud rate clock cycle. Since the internal clock Clk16X is 16 times the receiving/transmitting baud rate clock fre- quency, the Start bit needs to be low at least 8 Clk16X clocks to be considered as a valid Start bit.
Start Bit Detection
The receiver uses a 16X clock timing. The start bit could have occurred as much as one clock cycle before it was detected, as indicated by the shaded portion (A). The center of the start bit is defined as clock count 7 1/2. If the receiver clock is a symmetrical square wave, the center of the start bit will be located within 1/2 clock cycle, 1/32 bit or 3.125% giving a receiver margin of 46.875%. The receiver begins searching for the next start bit at the center of the first stop bit.
UART Control Register
The UART Control Register (UCR) is a write-only register. Writing a command word to the UCR configures the transmission and reception circuitry. The command word essentially describes the format of characters that are to be transmitted or received. The format of these characters are made up of (1) a specific word length, (2) parity information, and (3) a selected number of stop bits, used to indicate transmission of that character is completed.
Design Universal Asynchronous ReceiverTransmitter.docx (Size: 916.87 KB / Downloads: 63)
INTRODUCTION
This thesis portrays a novel architecture of Universal Asynchronous Receiver Transmitter. UARTs are used for asynchronous serial data communication between remote embedded systems. The UART is for interfacing computers or microprocessors to an asynchronous serial data channel. The receiver converts serial start, data, parity and stop bits. The transmitter converts parallel data into serial form and automatically adds start, parity and stop bits. The data word length can be 5, 6, 7 or 8 bits. Parity may be odd or even. Parity checking and generation can be inhibited. The stop bits may be one or two or one and one-half when transmitting 5-bit code.
Synchronous Serial Transmission
Synchronous serial transmission requires that the sender and receiver share a clock with one another, or that the sender provide a strobe or other timing signal so that the receiver knows when to “read” the next bit of the data. In most forms of serial Synchronous communication, if there is no data available at a given instant to transmit, a fill character must be sent instead so that data is always being transmitted. Synchronous communication is usually more efficient because only data bits are transmitted between sender and receiver, and synchronous communication can be more costly if extra wiring and circuits are required to share a clock signal between the sender and receiver.
Receiver Module
The serial receiver section also contains an 8-bit Receiver Buffer Register (RBR) and Receiver Shift Register (RSR). The status of RBR can be provided by either independent pin RxRDYn or the Receiver Data available flag (DR) in LSR.
Since the serial frame is asynchronous to the receiving clock, a high to low transition of SIN pin will be treated as the Start bit of a frame. However, in order to avoid receiving a incorrect data due to SIN signal noise, the False Start Bit Detection feature is implemented in the design which requires the Start bit to be low at least 50% of the receiv- ing baud rate clock cycle. Since the internal clock Clk16X is 16 times the receiving/transmitting baud rate clock fre- quency, the Start bit needs to be low at least 8 Clk16X clocks to be considered as a valid Start bit.
Start Bit Detection
The receiver uses a 16X clock timing. The start bit could have occurred as much as one clock cycle before it was detected, as indicated by the shaded portion (A). The center of the start bit is defined as clock count 7 1/2. If the receiver clock is a symmetrical square wave, the center of the start bit will be located within 1/2 clock cycle, 1/32 bit or 3.125% giving a receiver margin of 46.875%. The receiver begins searching for the next start bit at the center of the first stop bit.
UART Control Register
The UART Control Register (UCR) is a write-only register. Writing a command word to the UCR configures the transmission and reception circuitry. The command word essentially describes the format of characters that are to be transmitted or received. The format of these characters are made up of (1) a specific word length, (2) parity information, and (3) a selected number of stop bits, used to indicate transmission of that character is completed.