13-05-2014, 12:11 PM
BPSK, QPSK MODULATOR SIMULATION MODEL
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ABSTRACT
This project arised out of the diploma thesis called „BPSK, QPSK Modulator and Demo-
dulator“. Design facilities of the modulator in the FPGA are presented in this paper using a
VHDL language and DDS component in the Xilinx ISE development tool. The basic buil-
ding block is a DDS synthesizer accessible as an intelectual property core. The result is
a modulator simulation model with possibility of implementation in FPGA.
INTRODUCTION
The digital design was chosen because the advantages of a digital solution are apparent.
The main advantages of the digital solution are frequency agility, repeatibility, cost and the
simpler reconfiguration compared to analog as I experienced in my diploma thesis [1].
The reason why an FPGA was used is that the FPGA is highly configurable silicon engine,
with high MIPS (Mega Instruction Per Second) real-time signal processing functions.
Compared to the digital signal processors (DSP), FPGA are characterized by a high flexibi-
lity. The revolutionary evolution in FPGA technologies in last years allowed increasing ga-
te count, clock speed and integration of many functions like dedicated high-speed hardwa-
re multipliers and embedded processors.
The next chapter presents an analysis of the Phase Shift Keying (PSK) modulation. The
following chapter desribes the design of modulator. Next chapter refers to modulator map-
ping to the FPGA. The last chapter summarizes the whole process from analysis to creating
the simulation model.
ANALYSIS
PSK is a digital modulation where the carrier phase is keyed by the digital modulation sig-
nal. Two types of modulations, the BPSK and QPSK are desribed and used in this case.
In BPSK modulation the carrier phase acquires two discrete states (0° and 180°), which
correspond to one bit of the modulation signal. Therefore the symbol period is equal to the
bit period Ts = Tb.
SIMULATION
A simulation of the symbol mapper function is shown in Fig. 3. Signal din is an input da-
taflow timed by the input clock clk_b. Signal out_iq is an output of the symbol mapper into
the two channels. Signal bq switches the type of a modulation (BPSK, QPSK).
SUMMARY
The specific digital design from analysis over creating the simulation model to mapping
the modulator to the FPGA was shown in this paper. The simplicity of construction was re-
ached using intelectual property component in a combination with the VHDL language.
Properly configured and wired components created functional model, which is showed in
simulation diagrams. This model was finally mapped to a certain device.
The last step remained the configuration of this design to the physical FPGA structure.
Further aim is to create the functional model of demodulator and to control its DSP com-
ponents using the embedded processor.