15-09-2017, 01:09 PM
It is envisaged that sub-threshold leakage power will dominate the total power consumed by a CMD circuit in deep submicron technology (DSM). Circuit techniques designed to reduce leakage currents are therefore highly desirable. In this work, we propose low power CMOS designs with dual domino voltage logic (dual-Vt). Dual-threshold (single-Vt), double-Vt and double-Vt-modified logic circuits are compared with respect to power and speed. These design styles are compared by performing transistor-level simulations detailed in reference circuits using the DSCH3 tool and Microwind3 CAD.