06-04-2012, 04:18 PM
VHDL1
VHDL.ppt (Size: 610.5 KB / Downloads: 68)
Resource & references
Fundamentals of digital logic with VHDL design, Brown and Vranesic, Macgraw Hill 2000.
Foundation series software, XILINX student edition (contains a CDROM with design tools for Xilinx), Prentice Hall.
Concept of signals
A signal is used to carry logic information.
In hardware it is a wire.
A signal can be “in” or “out” ..etc.
There are many logic types of signals (wires)
Bit (can only have logic 1 or 0)
Std_logic can be 1, 0 , Z ..etc. ( Z=float.)
Std_logic_vector is a group of wires (called bus).
a, b: in std_logic_vector(3 downto 0); in VHDL
means a(0), a(1), a(2), a(3) are std_logic signals
Same for b.
IN, OUT, INOUT, BUFFER modes
IN: data flows in, like an input pin
OUT: data flows out, just like an output. The output cannot be read back by the entity
INOUT: bi-directional, used for data lines of a CPU etc.
BUFFER: similar to OUT but it can be read back by the entity. Used for control/address pins of a CPU etc.
Quick revision
You should know
Entity
Entity declaration
Use of port()
Modes of IO signals
Structure of a simple Architecture body
VHDL.ppt (Size: 610.5 KB / Downloads: 68)
Resource & references
Fundamentals of digital logic with VHDL design, Brown and Vranesic, Macgraw Hill 2000.
Foundation series software, XILINX student edition (contains a CDROM with design tools for Xilinx), Prentice Hall.
Concept of signals
A signal is used to carry logic information.
In hardware it is a wire.
A signal can be “in” or “out” ..etc.
There are many logic types of signals (wires)
Bit (can only have logic 1 or 0)
Std_logic can be 1, 0 , Z ..etc. ( Z=float.)
Std_logic_vector is a group of wires (called bus).
a, b: in std_logic_vector(3 downto 0); in VHDL
means a(0), a(1), a(2), a(3) are std_logic signals
Same for b.
IN, OUT, INOUT, BUFFER modes
IN: data flows in, like an input pin
OUT: data flows out, just like an output. The output cannot be read back by the entity
INOUT: bi-directional, used for data lines of a CPU etc.
BUFFER: similar to OUT but it can be read back by the entity. Used for control/address pins of a CPU etc.
Quick revision
You should know
Entity
Entity declaration
Use of port()
Modes of IO signals
Structure of a simple Architecture body