06-10-2012, 05:46 PM
VLSI Design
VLaSI.ppt (Size: 597.5 KB / Downloads: 39)
MOS Capcitances
Beyond the steady state behavior of the MOS transistor.
In order to examine the transient (AC) response of MOSFETs the digital circuits consisting of MOSFETs we have to determine the nature and amount of parasitic capacitances associated with the MOS transistor.
On chip capacitances found on MOS circuits are in general complicated functions of the layout geometries and the manufacturing processes.
Most of these capacitances are not lumped but distributed and their exact calculations would usually require complex three dimensional nonlinear charge-voltage models.
A lumped representation of the capacitance can be used to analyze the dynamic transient behavior of the device.
The capacitances can be classified as oxide related or junction capacitances and we will start the analysis with the oxide related capacitances.
MOS Oxide Capacitances
The gate-to-source capacitance is actually the gate-to-channel capacitance seen between the gate and the source terminals.
The gate-to-drain capacitance is actually the gate-to-channel capacitance seen between the gate and the drain terminals.
In Cut-off mode the surface is not inverted and there is no conducting channel linking the surface to the source and to the drain.
The gate-to-source and gate-to-drain capacitances are both equal to zero (Cgs=Cgd=0).
The gate-to-substrate capacitance can be approximated by: Cgb=CoxWL
In linear mode the inverted channel extends across the MOSFET between the source and drain. This conducting inversion layer on the surface effectively shields the substrate from the gate electric field making it Cgb=0.
Junction Capacitances
The n+ regions forms a number of planar pn-junctions with the surrounding p-type substrate numbered 1-5 on the diagram.
Planar junctions 2, 3 and 4 are surrounded by the p+ channel stop implant.
Planar junction 1 is facing the channel while the bottom planar junction 5 is facing the p-type substrate with doping NA.
The junction types will be n+/p, n+/p+, n+/p+ n+/p+ and n+/p.
VLaSI.ppt (Size: 597.5 KB / Downloads: 39)
MOS Capcitances
Beyond the steady state behavior of the MOS transistor.
In order to examine the transient (AC) response of MOSFETs the digital circuits consisting of MOSFETs we have to determine the nature and amount of parasitic capacitances associated with the MOS transistor.
On chip capacitances found on MOS circuits are in general complicated functions of the layout geometries and the manufacturing processes.
Most of these capacitances are not lumped but distributed and their exact calculations would usually require complex three dimensional nonlinear charge-voltage models.
A lumped representation of the capacitance can be used to analyze the dynamic transient behavior of the device.
The capacitances can be classified as oxide related or junction capacitances and we will start the analysis with the oxide related capacitances.
MOS Oxide Capacitances
The gate-to-source capacitance is actually the gate-to-channel capacitance seen between the gate and the source terminals.
The gate-to-drain capacitance is actually the gate-to-channel capacitance seen between the gate and the drain terminals.
In Cut-off mode the surface is not inverted and there is no conducting channel linking the surface to the source and to the drain.
The gate-to-source and gate-to-drain capacitances are both equal to zero (Cgs=Cgd=0).
The gate-to-substrate capacitance can be approximated by: Cgb=CoxWL
In linear mode the inverted channel extends across the MOSFET between the source and drain. This conducting inversion layer on the surface effectively shields the substrate from the gate electric field making it Cgb=0.
Junction Capacitances
The n+ regions forms a number of planar pn-junctions with the surrounding p-type substrate numbered 1-5 on the diagram.
Planar junctions 2, 3 and 4 are surrounded by the p+ channel stop implant.
Planar junction 1 is facing the channel while the bottom planar junction 5 is facing the p-type substrate with doping NA.
The junction types will be n+/p, n+/p+, n+/p+ n+/p+ and n+/p.