27-03-2012, 12:40 PM
Hardware Description Language
20477704-Hardware-Description-Language-HDL-Introduction-to-HDL.ppt (Size: 122 KB / Downloads: 64)
Introduction to HDL :
In electronics a HDL is a language from a class of computer language for formal description of electronic circuit.
It can describe circuit operation, its design and tests to verify its operation at any level
VHDL and VERILOG are popular HDL’s
Advantages of Hardware Description Language (HDL)
HDL’s has several advantages over traditional design methodology ,they are:
We can verify design functionality early in the design written as an HDL description.
Design simulation at this higher level before implementation at gate level, allow you to test architecture and design decision.
Reduced non-recurring engineering costs.
Design reused is enabled.
Increase flexibility to design changes.
Better and easier design auditing and verification.
Features of VHDL
VHDL has powerful constructs.
In VHDL, design may be decomposed hierarchically.
Each design element has a well defined interface useful for connecting it to other elements.
Each design element has a precise behavioral specification useful for simulating it.
VHDL handles asynchronous as well as synchronous sequential circuits.
In VHDL, timing and clocking can be modeled.
In VHDL, design is target independent.
VHDL supports design library.
The language is not case sensitive.
USE Clause
The use clause makes visible item specified as suffixes in selected names listed in the clause.
If a designer wants to have all declarations in a package visible, then the item clause should be substituted by the reserved word all.
The syntax of use clause is:
use library_name.package_name.item;
use library_name.package_name;
use library_name.package_name.all;
Structure of VHDL program:
Every VHDL program consists of at least one entity/architecture pair
Combination of an entity and its corresponding architecture is referred as a design entity.
In large design, you will typically write many entities/architecture pairs and connect them together to form a complete circuit.
An entity declaration describes the circuit as it appears from the “outside”- from the perspective of its input and output interfaces
The second part of the minimal VHDL design description is the architecture declaration
The architecture describes the actual function of the entity to which it bound