01-05-2012, 05:17 PM
Synchronous Timing
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Timing
Valid data must be present for a minimum amount of time prior to the input clock edge to guarantee successful capture of the data. This is setup time, Tsetup.
Data must remain valid for a minimum amount of time after the input clock edge to guarantee that the proper value is captured. This is the hold time, Thold.
Clock Skew
What happens if the clock signals at the source and destination are not in phase?
What if the clock arrives at the destination before it reaches the source? Vice-versa?
What are the sources of uncertainty in the phase relationship between different clock signals?
Clock Jitter – Causes & Effects
The net effect of clock jitter is that it can reduce the total delay that signals are allowed to have for a given frequency target.
i.e. jitter can reduce the clock cycle time, as illustrated by the diagrams on the previous page.
Clock jitter is caused by:
noise in the system that affects the response of the clock driver circuits.
noise in the system that affects the transmission characteristics of the signals.
Since they affect the operation we must consider clock skew and jitter in our timing analysis.
Synchronous Timing Summary
Synchronous memory elements require a stable data signal for a minimum amount of time prior to (SETUP) & after (HOLD) the input clock.
Hold and setup conditions determine the minimum and maximum system delays.
Setup and hold conditions can be analyzed by constructing timing loops in the timing diagrams.
Component delays exhibit variation across process and environmental conditions. Interconnect delays contain variations due to design and process.
Redefining driver and interconnect delays in terms of system and “spec” loads allows manufacturers to specify and test component delays.
System timing equations provide a key tool for examining trade-offs during system design.