21-09-2017, 02:56 PM
A delta-sigma analog-to-digital converter (ADC) is designed, optimized and simulated for converting column-level data into a CMOS image sensor. For a 0.18 mm process, the design reaches 80 dB signal-to-noise ratio (SNR), including a 10 dB margin for non-simulated kTC noise, and consumes 210 muW of power at a sampling frequency of 50 kHz . The low power is mainly realized using a architecture of first order and minimizing the capacitors. For the modulator, an optimized cascade folded-helmet (OTA) transconductance amplifier is optimized to achieve a gain of 90 dB with a unit gain bandwidth of 300 MHz. The decimator is also optimized by placing part of the circuit in the level of chip. Zero distortion is possible in the decimator due to the discrete time nature of the input signal. The proposed ADC allows a reduction in reading non-linearity of a CMOS image sensor, which allows a high SNR to be performed.