28-06-2012, 12:15 PM
Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop
Clock-Deskew Buffer.pdf (Size: 259.39 KB / Downloads: 49)
Abstract
A successive approximation register-controlled
delay-locked loop (SARDLL) has been fabricated in a 0.25- m
standard n-well DPTM CMOS process to realize a fast-lock
clock-deskew buffer for long distance clock distribution. This
DLL adopts a binary search method to shorten lock time while
maintaining tight synchronization between input and output
clocks. The measured lock time of the proposed SARDLL is within
30 clock cycles at 100-MHz clock input.
INTRODUCTION
WITH the rapid advances in semiconductor technologies,
modern digital systems operated at several hundred
megahertz have been successfully developed for many years.
Since there are more and more IC modules integrated on the
same printed-circuit board (PCB), the clock-skew problem will
undoubtedly be significant and becomes one of the bottlenecks
for high-performance systems. The clock-skew problem exists
in several different situations. For example, the input clock
driver in any chip will somewhat introduce uncertain time delay
between the internal clock and the external clock. Thus, the
internal clocks in a multi-chip system become asynchronous
and problems will occur when data transfer between chips is
needed. This phenomenon will also become more serious for
chips operated at gigahertz in the future. In addition, on a large
PCB, the length of traces between different chips and the clock
generator may differ from each other.
CONVENTIONAL DIGITAL DLL’S AND SARDLL
Fig. 2 shows the block diagram of the register-controlled DLL
(RDLL) [1], [4], [5]. The feedback clock signal is the delayed
version of the input clock signal, and the shift register controls
the amount of the delay time. The PC compares the phases of
the input clock signal and the output clock signal. The outputs of
the PC, Fast, Just, and Slow, are used to control the shift register.
The input clock signal is a common input for every delay stage.
At any time, only one bit of the shift register is active to select
a point of entry of the delay line for the input clock signal. The
number of the delay stages which the input clock signal goes
through determines total amount of delay. When Fast is active,
the feedback clock leads the input clock, and the high bit in the
shift register will be shifted left to increase the delay time.
CIRCUIT DESCRIPTION
The block diagram of the SARDLL is shown in Fig. 5. It
consists of a PC, a digital-controlled delay line as in the conventional
digital DLL’s, and an additional frequency divider, an
initial circuit (INCKT), and a 6-bit SAR [8], [9] to provide a
control word for the delay line. Again, two off-chip transmission
lines are involved in the clock-deskew system. Each block
in the SARDLL is described as follows.
CONCLUSION
In this paper, a low-voltage clock-deskew buffer fabricated in
a 0.25- m standard CMOS technology is presented. The clockdeskew
buffer utilizes a SARDLL technique. This architecture
uses a binary-search method to quickly find an optimal delay
time between the input and output clocks for clock synchronization,
and achieves short lock time.
Clock-Deskew Buffer.pdf (Size: 259.39 KB / Downloads: 49)
Abstract
A successive approximation register-controlled
delay-locked loop (SARDLL) has been fabricated in a 0.25- m
standard n-well DPTM CMOS process to realize a fast-lock
clock-deskew buffer for long distance clock distribution. This
DLL adopts a binary search method to shorten lock time while
maintaining tight synchronization between input and output
clocks. The measured lock time of the proposed SARDLL is within
30 clock cycles at 100-MHz clock input.
INTRODUCTION
WITH the rapid advances in semiconductor technologies,
modern digital systems operated at several hundred
megahertz have been successfully developed for many years.
Since there are more and more IC modules integrated on the
same printed-circuit board (PCB), the clock-skew problem will
undoubtedly be significant and becomes one of the bottlenecks
for high-performance systems. The clock-skew problem exists
in several different situations. For example, the input clock
driver in any chip will somewhat introduce uncertain time delay
between the internal clock and the external clock. Thus, the
internal clocks in a multi-chip system become asynchronous
and problems will occur when data transfer between chips is
needed. This phenomenon will also become more serious for
chips operated at gigahertz in the future. In addition, on a large
PCB, the length of traces between different chips and the clock
generator may differ from each other.
CONVENTIONAL DIGITAL DLL’S AND SARDLL
Fig. 2 shows the block diagram of the register-controlled DLL
(RDLL) [1], [4], [5]. The feedback clock signal is the delayed
version of the input clock signal, and the shift register controls
the amount of the delay time. The PC compares the phases of
the input clock signal and the output clock signal. The outputs of
the PC, Fast, Just, and Slow, are used to control the shift register.
The input clock signal is a common input for every delay stage.
At any time, only one bit of the shift register is active to select
a point of entry of the delay line for the input clock signal. The
number of the delay stages which the input clock signal goes
through determines total amount of delay. When Fast is active,
the feedback clock leads the input clock, and the high bit in the
shift register will be shifted left to increase the delay time.
CIRCUIT DESCRIPTION
The block diagram of the SARDLL is shown in Fig. 5. It
consists of a PC, a digital-controlled delay line as in the conventional
digital DLL’s, and an additional frequency divider, an
initial circuit (INCKT), and a 6-bit SAR [8], [9] to provide a
control word for the delay line. Again, two off-chip transmission
lines are involved in the clock-deskew system. Each block
in the SARDLL is described as follows.
CONCLUSION
In this paper, a low-voltage clock-deskew buffer fabricated in
a 0.25- m standard CMOS technology is presented. The clockdeskew
buffer utilizes a SARDLL technique. This architecture
uses a binary-search method to quickly find an optimal delay
time between the input and output clocks for clock synchronization,
and achieves short lock time.