02-11-2012, 11:52 AM
SIMULATION OF PARALLEL ADDER
SIMULATION OF PARALLEL.doc (Size: 38 KB / Downloads: 32)
AIM:
To design and simulate the pipelined parallel adder to add eight 12bit numbers using 2’s complement.
APPARATUS REQUIRED:
• XILINX ISE 9.2i software
• PC with Windows-XP
ALGORITHM:
• Create a verilog file
• Assign port names
• Write verilog program
• Check syntax
• Create a test bench waveform and give input
• Simulate the parallel adder using ISE simulator
THEORY:
Parallel adder is an adder which adds all the n-bits of
m-numbers at a time. Two’s compliment of a binary number is calculated as follows,
• Take a binary number which is having one more bit then the number for which we are going to find 2’s compliment.
• The MSB of the number should be one and the LSB of the number should be zero.
• To get 2’s compliment we have to subtract the two numbers.
• After finding the 2’s compliment we have to add all the numbers.
• Take 2’s compliment for the above result to get original result.