14-11-2012, 05:46 PM
Circuit Characterization and Performance Estimation
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CMOS Inverter Switching Characteristics
Define:
Rise time tr = time required for a node to charge from the 10% point to 90% point
Fall time tf = time required for a node to discharge from 90% to 10% point
Delay time td = delay from the 50% point on the input to the 50% point on the output
Falling delay tdf = delay time with output falling
Rising delay tdr = delay time with output rising
CMOS Inverter Driving a Lumped Capacitance Load
CMOS Inverter can be viewed as a single transistor either charging the Cload or discharging the Cload
Vin is assumed to switch abruptly
If Vin switches high, the NMOS Tx discharges Cload while the PMOS Tx turns OFF
If Vin switches low, the PMOS Tx charges Cload while the NMOS Tx turns OFF
Cload is comprised of
Cgate due to the gate capacitance of receiving circuits
Cwire of the interconnect metal
Cdiffusion of the inverter output junctions
Transient Response:
Approximate as a simple RC network where R is given as an equivalent resistance of the NMOS and PMOS devices and C is given as the total lumped Cload capacitance
CMOS Inverter Propagation Delay Summary
Summing the two delay components from the previous chart, we obtain the expression (at left) for the propagation delay (high-to low) for an NMOS transistor discharging CL
For CMOS, VOH = VDD and VOL = 0, so the propagation delay (output falling) becomes the expression shown (at left)
A similar expression (left) is obtained by considering the derivation of charging Cload with the PMOS transistor when the input abruptly falls from VDD to 0 and the output rises (low-to-high propagation delay)
Transistors in Series: CMOS NAND
Several devices in series each with effective channel length Leff can be viewed as a single device of channel length equal to the combined channel lengths of the separate series devices
e.g. 3 input NAND: a single device of channel length equal to 3Leff could be used to model the behavior of three series devices each with Leff channel length, assuming there is no skew in the increasing gate voltage of the three N pull-down devices.
The source/drain junctions between the three devices essentially are assumed as simple zero resistance connections
During saturation transient, the bottom two devices will be in their linear region and only the top device will be pinched off.