20-09-2017, 01:08 PM
In electronics a sampling and retention circuit is an analog device that samples (captures, seizes) the voltage from an analog signal that varies continuously and maintains (blocks, freezes) its value at a constant level for a specified minimum period. Sampling and retaining circuits and related peak detectors are elementary analog memory devices. They are typically used in analog-to-digital converters to eliminate variations in the input signal that may damage the conversion process.
A typical sampling and retention circuit stores the electric charge in a capacitor and contains at least one switching device such as a FET switch (field effect transistor) and usually an operational amplifier. To sample the input signal, the switch connects the capacitor to the output of a buffer amplifier. The buffer amplifier charges or discharges the capacitor so that the voltage across the capacitor is nearly equal to or proportional to the input voltage. In standby mode, the switch disconnects the capacitor from the buffer. The capacitor is invariably discharged by its own leakage currents and payload currents, which makes the circuit inherently volatile, but the voltage loss (voltage drop) within a specified timeout remains within a margin of error acceptable.
Sampling and retention circuits are used in linear systems. In some types of analog-to-digital converters, the input is compared to an internally generated voltage from a digital-to-analog converter (DAC). The circuit attempts a series of values and stops converting once the voltages are equal, within a defined margin of error. If the input value were allowed to change during this comparison process, the resulting conversion would be inaccurate and possibly unrelated to the true input value. Such successive approach converters will often incorporate internal sampling and retention circuitry. In addition, sampling and retention circuits are often used when multiple samples need to be measured at the same time. Each value is sampled and retained, using a common sample clock.
For virtually all commercial liquid crystal active matrix monitors based on TN, IPS or VA electro-optical cells (excluding bi-stable phenomena), each pixel represents a small capacitor that has to be periodically charged at a level corresponding to the scale value of gray (contrast) for an image element. In order to maintain the level during a scan cycle (frame period), an additional electric capacitor is connected in parallel to each LC pixel to better retain the voltage. A thin film FET switch is directed to select a particular LC pixel and load the image information therefor. In contrast to an S / H in general electronics, there is no operational output amplifier and no electrical signal AO. Instead, the charge on the retention capacitors controls the deformation of the LC molecules and hence the optical effect as their output. The invention of this concept and its implementation in thin film technology have been honored with the IEEE Jun-ichi Nishizawa Medal in 2011.
During a scan cycle, the image does not follow the input signal. This does not allow the eye to cool and can lead to blurring during motion sequences, also the transition is visible between frames because the backlight is constantly illuminated, adding to display motion blur.
A typical sampling and retention circuit stores the electric charge in a capacitor and contains at least one switching device such as a FET switch (field effect transistor) and usually an operational amplifier. To sample the input signal, the switch connects the capacitor to the output of a buffer amplifier. The buffer amplifier charges or discharges the capacitor so that the voltage across the capacitor is nearly equal to or proportional to the input voltage. In standby mode, the switch disconnects the capacitor from the buffer. The capacitor is invariably discharged by its own leakage currents and payload currents, which makes the circuit inherently volatile, but the voltage loss (voltage drop) within a specified timeout remains within a margin of error acceptable.
Sampling and retention circuits are used in linear systems. In some types of analog-to-digital converters, the input is compared to an internally generated voltage from a digital-to-analog converter (DAC). The circuit attempts a series of values and stops converting once the voltages are equal, within a defined margin of error. If the input value were allowed to change during this comparison process, the resulting conversion would be inaccurate and possibly unrelated to the true input value. Such successive approach converters will often incorporate internal sampling and retention circuitry. In addition, sampling and retention circuits are often used when multiple samples need to be measured at the same time. Each value is sampled and retained, using a common sample clock.
For virtually all commercial liquid crystal active matrix monitors based on TN, IPS or VA electro-optical cells (excluding bi-stable phenomena), each pixel represents a small capacitor that has to be periodically charged at a level corresponding to the scale value of gray (contrast) for an image element. In order to maintain the level during a scan cycle (frame period), an additional electric capacitor is connected in parallel to each LC pixel to better retain the voltage. A thin film FET switch is directed to select a particular LC pixel and load the image information therefor. In contrast to an S / H in general electronics, there is no operational output amplifier and no electrical signal AO. Instead, the charge on the retention capacitors controls the deformation of the LC molecules and hence the optical effect as their output. The invention of this concept and its implementation in thin film technology have been honored with the IEEE Jun-ichi Nishizawa Medal in 2011.
During a scan cycle, the image does not follow the input signal. This does not allow the eye to cool and can lead to blurring during motion sequences, also the transition is visible between frames because the backlight is constantly illuminated, adding to display motion blur.