27-12-2012, 11:44 AM
D-FLIP FLOP MODEL
Problem Statement:
Study the parameters of a D Flip-Flop and write an accurate model of the same. Warnings should be displayed as a small description on the command window. The following parameters should be included in the model.
a. Setup time violation check.
b. Hold time violation check.
c. Reset recovery violation check.
d. Clock width violation check.
e. Clock to output delay for high to low o/p transition.
f. Clock to output delay for low to high o/p transition.
Block Diagram Description:
As shown in the block diagram, there are four inputs given to D flip flop. Here reset signal is major signal input to D ff. Whenever reset signal is high, output will be low. When reset signal is low and with that if enable and load are high, then and then only input is assigned to output signal Q.
Verification Strategy
We have verified Design using following strategies
1. Graphical User Interface.
2. Command Line.