16-01-2013, 03:19 PM
Low power High Efficient Hardware Implementation of Network Security Algorithm
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Abstract:
This paper discusses a Verilog implementation of the Advanced Encryption Standard (AES). AES
is based on the block cipher Rijndael algorithm. Rijndael algorithm is strong in any known attacks.
Moreover, it can be efficiently implemented in both hardware and software. We implemented Rijndael
algorithm in hardware, because hardware implementation gives faster encryption & decryption speed and
more physically secure. In this work, design and implementation of three configurable and flexible cores of
Rijndael algorithm are done: an encryptor, a decryptor, and both cores. These cores support not only the
AES, but also the whole Rijndael algorithm. We implemented Rijndael algorithm for 128 bits, 192 bits, and
256 bits key size with Verilog, synthesized with Xilinx, and simulated with ModelSim.
INTRODUCTION:
Security is a great necessity in data
operations today. The authentication process
or commerce exchanges need security and
reliability. There are several ways to
guarantee the operation of these systems
with security. Cryptography is one option
and is very used today in many applications.
One such scheme which helps in secured
data transaction is Advanced Encryption
Standard (AES). It was intended to replace
Triple DES, itself an interim fix for the
aging Data Encryption Standard (DES). The
DES has relatively small key and also it is
slow in hardware implementation. Simillarly
Tripple DES is slower in hardware
implementation. To overcome these
shortcomings AES was introduced.
Rijndael Algorithm:
Rijndael algorithm was submitted
by Vincent Rijmen and Joan Daemen. It is a
key-iterated block cipher performing
encryption and decryption for 128 bits input
data and private key cipher which uses same
key in data encryption and data decryption
operation for 128 bits, 192 bits, 256 bits key
size.
Encryption Algorithm:
In the Encryption part, first the
data block to be encrypted is split into an
array of bytes as shown in Fig-2. This
algorithm is based on round function,
and different combinations of the
algorithm are structured by repeating the
round function different times. Each
round function contains uniform and
parallel four steps: SubBytes, ShiftRows,
MixColumn and AddRoundKey
transformation and each step has its own
particular functionality.
Architecture of Rijndael Algorithm:
Here we present the
implementation of Rijndael in three
ways: the first one just encrypts the data,
the second one just decrypt and the third
one does the both executions. This
option can provide a choice to
implement the Rijndael, as the area
increases with the both devices together.
If either decrypt or encrypt function are
not needed, just one device could be
implemented. Although, the use of the
third implementation is better as it is
easiest to operate. All versions use a
very similar structure.
Conclusions:
This paper describes the Rijndael
implementation methods for 128 bits,
192 bits and 256 bits key size, and
synthesizing results. This
implementation needs less
supplementary registers and delicate key
control unlike separate AES-128
implementation, AES-192
implementation, and AES-256
implementation. Lookup table method is
applied to S-box implementation.
Therefore, we obtained moderate gate
counts and high speed Rijndael.