10-04-2013, 03:31 PM
ARITHMETIC AND LOGIC UNIT
AIM:
To develop the source code for arithmetic and logic unit by using VHDL/VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA.
THEORY:
The 74181 can be modeled as above. Recognizing the logic that makes up a CLA block in this case, the circled elements in the gate-level schematic is the key step in unraveling the secrets of the 74181. The four boxed circuits in the gate-level schematic are represented above by the single module M1 with 4-bit I/O buses. The second quadruplicated circuit in the 74181 leads to the high-level module M2. The various XOR gates are also grouped into 4-bit word gates as indicated above. Further analysis shows that the 74181 is original designers cleverly constructed the M1 and M2 logic so that with input line M = 1, each setting of the S (function select) bus produces one of the 16 possible Boolean functions of the form F(A,B).
PROCEDURE:
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench. Step7: Obtain the place and route report.