19-06-2013, 12:41 PM
Dynamic partial reconfiguration in FPGAs
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Abstract
Dynamic parital reconfigurable FPGAs offer new
design space with a variety of benefits: reduce the
configuration time and save memory as the partial
reconfiguration files (bitstreams) are smaller than full ones.
This paper introduces a simple reconfigurable system and
focuses on the advantages of the newest dynamic partial
reconfiguration design flow.
INTRODUCTION
Since 80’s the Field Programmable Gate Array (FPGA)
market growing rapidly with varied of application in
different industries.Their great advantage is their flexibility
that arises from their programmable nature as compared to
systems using application specific integrated circuits
(ASICs).There is a new concept evolving in FPGA
industry.The so-called dynamic partial reconfiguration(DPR)
can be exploited in many application fields,for instance to
fulfill space requirements in small portable systems, to create
a system-on-a-chip with a very high level of flexibility, to
realize adaptive hardware algorithms,and so on.
Section 2 describes the definition of dynamic partial
reconfiguration and two different methods are compared.The
advantages of the newest design flow is analysed in
Sect.3,the proposed DPR system is also presented in this
section.Section 4 describes the implementation design flow
of the experimental system on the FPGA platform.In
Sect.5,the results of the experiment is presented.Finally,the
conclusion is given in Sect.6.
Several styles of DPR
Xilinx inc. suggests in [2] two basic styles of dynamic
reconfiguration on a single FPGA: the Difference-based
partial reconfiguration and the module-based partial
reconfiguration.
Difference-based partial reconfiguration can be used
when a small change is made to the design. It is especially
useful in case of changing Look-Up Table (LUT) equations
or dedicated memory blocks content. The partial bitstream
contains only information about differences between the
current design structure (that resides in the FPGA) and the
new content of an FPGA.
Description of the design in this paper
This paper presents a DPR system using the EAPR
flow.In this system, a Gray counter and a Johnson counter
are reconfigurated dynamically on a Xilinx Virtex4-FX12
FPGA chip. The output part is four leds,which are used to
demonstrate the counter.The proposed EAPR-based system
architecture is shown in Fig.3.This system consists of a led
control module and two partial reconfiguration
modules(PRM A1, PRM A2)which are placed on the same
partial reconfiguration region. The led control module which
enable the leds is a part of the static module.
RESULTS
Firstly,the full bitstream is downloaded to initial the
device,then,the partial bitstreams are downloaded when the
FPGA is running,meanwhile,the leds light along with the
choosed partial bitstreams.The full bitstream is 582KB,while
the partil bitstream is 12KB for Gray counter and 12KB for
Johnson counter.Since the size of the bitstream is directly
proportional to the number of resources being
configured[8],partial reconfiguration utilizes a smaller
bitstream than a full bitstream for the FPGA. The direct
benefit is less space needed for storing the necessary
configurations for operation.As reconfiguration times are
highly dependent on the size and organization of the PRRs,
an additional benefit is that the reconfiguration time is
shorter.
CONCLUSION
In this paper,we have illustrate the clear advantage of
EAPR flow over the XAPP290.Then,we design a experiment
based on EAPR to proof that this method can decrease the
size of bitstreams obviously.
Recently,Xilinx presented a new tool called PlanAhead
to support the EAPR design flow[9,10], this software is the
first graphical environment for partial reconfiguration. Using
PlanAhead design tools as a platform for partial
reconfiguration applications can greatly simplify the
complexities of the dynamic operating environment.