13-12-2012, 03:23 PM
VLSI System Design
Logical Effort and Transistor Sizing.pdf (Size: 118.29 KB / Downloads: 25)
Introduction
Chip designers face a bewildering array of choices
– What is the best circuit topology for a function?
– How many stages of logic give least delay?
How wide should the transistors be?
Logical effort is a method to make these
decisions
– Uses a simple model of delay
– Allows back-of-the-envelope calculations
– Helps make rapid comparisons between
alternatives
Delay in a Logic Gate
Represents delay of gate driving no load
–Set by internal parasitic capacitance
Logical Effort and Transistor Sizing.pdf (Size: 118.29 KB / Downloads: 25)
Introduction
Chip designers face a bewildering array of choices
– What is the best circuit topology for a function?
– How many stages of logic give least delay?
How wide should the transistors be?
Logical effort is a method to make these
decisions
– Uses a simple model of delay
– Allows back-of-the-envelope calculations
– Helps make rapid comparisons between
alternatives
Delay in a Logic Gate
Represents delay of gate driving no load
–Set by internal parasitic capacitance