29-11-2012, 05:58 PM
A Versatile FPGA-based High Speed Bit Error Rate Testing Scheme
A Versatile FPGA.pdf (Size: 694.97 KB / Downloads: 228)
Abstract
FPGAs have witnessed an increased use of dedicated communication interfaces. With
their increased use, it is becoming critical to test and properly characterize all such
interfaces. Bit error rate (BER) characteristic is one of the basic measures of the
performance of any digital communication system. Traditionally, BER is evaluated using
Monte-Carlo simulations, which are very time-consuming. Though there are some BER
test products, none of them includes channel emulator. To overcome these problems, this
thesis presents a scheme for BER testing in FPGAs, with a few orders of magnitude
speedup compared to Monte-Carlo method. This scheme consists of two intellectual
property (IP) cores: the BER tester (BERT) core and the additive white Gaussian noise
(AWGN) generator core. Two challenging testing cases are successfully conducted using
the testing scheme. We demonstrate through case studies that the proposed BER testing
solution exhibits advantages in speed and cost compared with the existing solutions.
Introduction
Motivation
FPGA Perspective
As FPGAs and the associated design software have evolved to include multimillion gates,
specialized communication interfaces, such as clock data recovery (CDR) circuitry and
enhanced phase-locked loops (PLLs), are increasingly being included in FPGAs for highspeed
communication applications. Additionally, the performance and capacity
improvements of FPGAs give their users sufficient processing power to implement a wide
range of communication interfaces, including various wireline and wireless modulation
schemes, modern turbo error correcting codes and spread spectrum schemes. In
consequence, FPGA-based designs are more and more widely used in digital
communication systems to replace ASIC implementations.
Among these FPGA new features, high-frequency serial communication interfaces are
probably the most important. They are mostly realized using CDR circuits to extract the
clock from a data stream. Specialized CDR circuitry in Altera Mercury devices provides
data rates of up to 1.25 gigabits per second (Gbps) per channel, and total CDR bandwidth
of 45 Gbps [1]; the rate increases to 3.125 Gbps per channel in Altera Stratix GX devices.
Lattice Semiconductor’s Field Programmable System Chip (FPSC) includes 10 Gbps line
interfaces in ORLI10G and 1.5625 Gbps per channel CDR subsystems in ORT82G5 [2].
Xilinx’s Virtex-II Pro FPGAs provide up to twenty-four 3.125 Gbps full duplex Rocket
I/O transceivers, with an aggregate baud rate of up to 75 Gbps [3]. In consequence,
FPGA-based serial communication interfaces are being widely adopted into backplane
applications, short and long-haul communications, mass storage access networking, and
computer peripherals. However, the testing of gigabit-rate serializer and deserializer
(SerDes) devices is still challenging.
BER Testing Perspective
Bit error rate (BER) is the ratio of the number of incorrect to the total number of received
bits. For qualifying the reliability of an entire digital communication system from “bits
in” to “bits out”, BER characteristic is the fundamental measure of the performance of a
digital communication system.
As shown in Figure 1-1, a digital communication system consists of a transmitter, a
channel, and a receiver. The transmitter changes the raw information (sequences of binary
digits) into a format that is matched to the characteristics of the channel. Depending on
applications, the transmitter may consist of a source encoder, an encryptor, a channel
encoder, a carrier modulator or a spread-spectrum modulator.
BER and SNR
Among the factors discussed in Chapter 2.1.1, noise is the main enemy of BER
performance. The noise introduced by a communication system is usually described by a
Gaussian probability density function. Representing the function mathematically makes it
possible to predict the BER performance of the system.
As the ratio of the number of incorrect and the total number of received bits, BER is
related both theoretically and practically (by measurements) to the signal-to-noise ratio
(SNR). SNR is the fundamental input quantity that determines the channel capacity C for
a given bandwidth B, according to the fundamental Shannon law:
log (1 ) 2 C = B + SNR
In practice, communication system designers balance between bandwidth and SNR to
maximize the channel capacity for an acceptable BER performance. There are several
types of communication systems in which this balancing act is played in different ways.